📄 os_cpu_c.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\os_cpu_c.o --depend=.\rvmdk\os_cpu_c.d --device=DARMP --apcs=interwork -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\ARM\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\uCOSView\Source -I..\..\..\..\..\uCOSView\Ports\ARM7\LPC2000\IAR -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\ARM\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -IC:\Keil\ARM\INC\Philips --omf_browse=.\rvmdk\os_cpu_c.crf ..\..\..\..\..\uCOS-II\Ports\ARM\Generic\RealView\os_cpu_c.c]
ARM
AREA ||.text||, CODE, READONLY, ALIGN=2
OSInitHookBegin PROC
;;;132 #if OS_TMR_EN > 0
;;;133 OSTmrCtr = 0;
000000 e59f114c LDR r1,|L1.340|
000004 e3a00000 MOV r0,#0
000008 e1c100b0 STRH r0,[r1,#0] ; OSTmrCtr
;;;134 #endif
;;;135 }
00000c e12fff1e BX lr
;;;136 #endif
ENDP
OSInitHookEnd PROC
;;;159 #endif
;;;160 }
000010 e12fff1e BX lr
;;;161 #endif
ENDP
OSTaskCreateHook PROC
;;;193 #if OS_APP_HOOKS_EN > 0
;;;194 App_TaskCreateHook(ptcb);
000014 eafffffe B App_TaskCreateHook
;;;195 #else
;;;196 (void)ptcb; /* Prevent compiler warning */
;;;197 #endif
;;;198 }
;;;199 #endif
ENDP
OSTaskDelHook PROC
;;;224 #if OS_APP_HOOKS_EN > 0
;;;225 App_TaskDelHook(ptcb);
000018 eafffffe B App_TaskDelHook
;;;226 #else
;;;227 (void)ptcb; /* Prevent compiler warning */
;;;228 #endif
;;;229 }
;;;230 #endif
ENDP
OSTaskIdleHook PROC
;;;251 #if OS_APP_HOOKS_EN > 0
;;;252 App_TaskIdleHook();
00001c eafffffe B App_TaskIdleHook
;;;253 #endif
;;;254 }
;;;255 #endif
ENDP
OSTaskStatHook PROC
;;;271 #if OS_APP_HOOKS_EN > 0
;;;272 App_TaskStatHook();
000020 eafffffe B App_TaskStatHook
;;;273 #endif
;;;274 }
;;;275 #endif
ENDP
OSTaskStkInit PROC
;;;313 stk = ptos; /* Load stack pointer */
;;;314 task_addr = (INT32U)task & ~1; /* Mask off lower bit in case task is thumb mode */
000024 e3c03001 BIC r3,r0,#1
;;;315 *(stk) = (INT32U)task_addr; /* Entry Point */
000028 e5823000 STR r3,[r2,#0]
;;;316 *(--stk) = (INT32U)0x14141414L; /* R14 (LR) */
00002c e59f3124 LDR r3,|L1.344|
;;;317 *(--stk) = (INT32U)0x12121212L; /* R12 */
;;;318 *(--stk) = (INT32U)0x11111111L; /* R11 */
;;;319 *(--stk) = (INT32U)0x10101010L; /* R10 */
;;;320 *(--stk) = (INT32U)0x09090909L; /* R9 */
;;;321 *(--stk) = (INT32U)0x08080808L; /* R8 */
;;;322 *(--stk) = (INT32U)0x07070707L; /* R7 */
;;;323 *(--stk) = (INT32U)0x06060606L; /* R6 */
;;;324 *(--stk) = (INT32U)0x05050505L; /* R5 */
;;;325 *(--stk) = (INT32U)0x04040404L; /* R4 */
;;;326 *(--stk) = (INT32U)0x03030303L; /* R3 */
;;;327 *(--stk) = (INT32U)0x02020202L; /* R2 */
;;;328 *(--stk) = (INT32U)0x01010101L; /* R1 */
;;;329 *(--stk) = (INT32U)p_arg; /* R0 : argument */
;;;330 if ((INT32U)task & 0x01) { /* See if task runs in Thumb or ARM mode */
000030 e3100001 TST r0,#1
000034 e5023004 STR r3,[r2,#-4] ;316
000038 e59f311c LDR r3,|L1.348|
00003c e2420038 SUB r0,r2,#0x38
000040 e5023008 STR r3,[r2,#-8] ;317
000044 e59f3114 LDR r3,|L1.352|
000048 e502300c STR r3,[r2,#-0xc] ;318
00004c e59f3110 LDR r3,|L1.356|
000050 e5023010 STR r3,[r2,#-0x10] ;319
000054 e59f310c LDR r3,|L1.360|
000058 e5023014 STR r3,[r2,#-0x14] ;320
00005c e1c331c3 BIC r3,r3,r3,ASR #3 ;321
000060 e5023018 STR r3,[r2,#-0x18] ;321
000064 e04331c3 SUB r3,r3,r3,ASR #3 ;322
000068 e502301c STR r3,[r2,#-0x1c] ;322
00006c e1c33143 BIC r3,r3,r3,ASR #2 ;323
000070 e5023020 STR r3,[r2,#-0x20] ;323
000074 e02330c3 EOR r3,r3,r3,ASR #1 ;324
000078 e5023024 STR r3,[r2,#-0x24] ;324
00007c e1c33143 BIC r3,r3,r3,ASR #2 ;325
000080 e5023028 STR r3,[r2,#-0x28] ;325
000084 e0433143 SUB r3,r3,r3,ASR #2 ;326
000088 e502302c STR r3,[r2,#-0x2c] ;326
00008c e1c330c3 BIC r3,r3,r3,ASR #1 ;327
000090 e5023030 STR r3,[r2,#-0x30] ;327
000094 e1a030c3 ASR r3,r3,#1 ;328
000098 e880000a STM r0,{r1,r3}
00009c e2422038 SUB r2,r2,#0x38
;;;331 *(--stk) = (INT32U)ARM_SVC_MODE_THUMB; /* CPSR (Enable both IRQ and FIQ interrupts, THUMB-mode) */
;;;332 } else {
;;;333 *(--stk) = (INT32U)ARM_SVC_MODE_ARM; /* CPSR (Enable both IRQ and FIQ interrupts, ARM-mode) */
0000a0 03a01013 MOVEQ r1,#0x13
0000a4 13a01033 MOVNE r1,#0x33 ;331
0000a8 e2420004 SUB r0,r2,#4 ;331
0000ac e5021004 STR r1,[r2,#-4] ;331
;;;334 }
;;;335
;;;336 return (stk);
;;;337 }
0000b0 e12fff1e BX lr
;;;338
ENDP
OSTaskSwHook PROC
;;;379 #if OS_APP_HOOKS_EN > 0
;;;380 App_TaskSwHook();
0000b4 eafffffe B App_TaskSwHook
;;;381 #endif
;;;382 }
;;;383 #endif
ENDP
OSTCBInitHook PROC
;;;399 #if OS_APP_HOOKS_EN > 0
;;;400 App_TCBInitHook(ptcb);
0000b8 eafffffe B App_TCBInitHook
;;;401 #else
;;;402 (void)ptcb; /* Prevent compiler warning */
;;;403 #endif
;;;404 }
;;;405 #endif
ENDP
OSTimeTickHook PROC
;;;420 void OSTimeTickHook (void)
;;;421 {
0000bc e92d4010 PUSH {r4,lr}
;;;422 #if OS_APP_HOOKS_EN > 0
;;;423 App_TimeTickHook();
0000c0 ebfffffe BL App_TimeTickHook
;;;424 #endif
;;;425
;;;426 #if OS_TMR_EN > 0
;;;427 OSTmrCtr++;
0000c4 e59f0088 LDR r0,|L1.340|
0000c8 e1d010b0 LDRH r1,[r0,#0] ; OSTmrCtr
0000cc e2811001 ADD r1,r1,#1
0000d0 e1c010b0 STRH r1,[r0,#0] ; OSTmrCtr
;;;428 if (OSTmrCtr >= (OS_TICKS_PER_SEC / OS_TMR_CFG_TICKS_PER_SEC)) {
0000d4 e1d010b0 LDRH r1,[r0,#0] ; OSTmrCtr
0000d8 e351000a CMP r1,#0xa
;;;429 OSTmrCtr = 0;
0000dc 23a01000 MOVCS r1,#0
0000e0 21c010b0 STRHCS r1,[r0,#0] ; OSTmrCtr
;;;430 OSTmrSignal();
0000e4 28bd4010 POPCS {r4,lr}
0000e8 2afffffe BCS OSTmrSignal
;;;431 }
;;;432 #endif
;;;433
;;;434 #if OS_CPU_ARM_DCC_EN > 0
;;;435 OSDCC_Handler();
;;;436 #endif
;;;437 }
0000ec e8bd4010 POP {r4,lr}
0000f0 e12fff1e BX lr
;;;438 #endif
ENDP
OS_CPU_InitExceptVect PROC
;;;506
;;;507 (*(INT32U *)OS_CPU_ARM_EXCEPT_UNDEF_INSTR_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
0000f4 e59f1070 LDR r1,|L1.364|
;;;508 (*(INT32U *)OS_CPU_ARM_EXCEPT_UNDEF_INSTR_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptUndefInstrHndlr;
0000f8 e59f2070 LDR r2,|L1.368|
0000fc e3a00000 MOV r0,#0 ;507
;;;509
;;;510 (*(INT32U *)OS_CPU_ARM_EXCEPT_SWI_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
000100 e5801004 STR r1,[r0,#4]
000104 e5802024 STR r2,[r0,#0x24]
;;;511 (*(INT32U *)OS_CPU_ARM_EXCEPT_SWI_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptSwiHndlr;
000108 e59f2064 LDR r2,|L1.372|
;;;512
;;;513 (*(INT32U *)OS_CPU_ARM_EXCEPT_PREFETCH_ABORT_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
00010c e5801008 STR r1,[r0,#8]
000110 e5802028 STR r2,[r0,#0x28]
;;;514 (*(INT32U *)OS_CPU_ARM_EXCEPT_PREFETCH_ABORT_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptPrefetchAbortHndlr;
000114 e59f205c LDR r2,|L1.376|
;;;515
;;;516 (*(INT32U *)OS_CPU_ARM_EXCEPT_DATA_ABORT_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
000118 e580100c STR r1,[r0,#0xc]
00011c e580202c STR r2,[r0,#0x2c]
;;;517 (*(INT32U *)OS_CPU_ARM_EXCEPT_DATA_ABORT_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptDataAbortHndlr;
000120 e59f2054 LDR r2,|L1.380|
;;;518
;;;519 (*(INT32U *)OS_CPU_ARM_EXCEPT_ADDR_ABORT_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
000124 e5801010 STR r1,[r0,#0x10]
000128 e5802030 STR r2,[r0,#0x30]
;;;520 (*(INT32U *)OS_CPU_ARM_EXCEPT_ADDR_ABORT_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptAddrAbortHndlr;
00012c e59f204c LDR r2,|L1.384|
;;;521
;;;522 (*(INT32U *)OS_CPU_ARM_EXCEPT_IRQ_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
000130 e5801014 STR r1,[r0,#0x14]
000134 e5802034 STR r2,[r0,#0x34]
;;;523 (*(INT32U *)OS_CPU_ARM_EXCEPT_IRQ_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptIrqHndlr;
000138 e59f2044 LDR r2,|L1.388|
;;;524
;;;525 (*(INT32U *)OS_CPU_ARM_EXCEPT_FIQ_VECT_ADDR) = OS_CPU_ARM_INSTR_JUMP_TO_HANDLER;
00013c e5801018 STR r1,[r0,#0x18]
000140 e5802038 STR r2,[r0,#0x38]
000144 e580101c STR r1,[r0,#0x1c]
;;;526 (*(INT32U *)OS_CPU_ARM_EXCEPT_FIQ_HANDLER_ADDR) = (INT32U)OS_CPU_ARM_ExceptFiqHndlr;
000148 e59f1038 LDR r1,|L1.392|
00014c e580103c STR r1,[r0,#0x3c]
;;;527 }
000150 e12fff1e BX lr
ENDP
|L1.340|
000154 00000000 DCD ||.data||
|L1.344|
000158 14141414 DCD 0x14141414
|L1.348|
00015c 12121212 DCD 0x12121212
|L1.352|
000160 11111111 DCD 0x11111111
|L1.356|
000164 10101010 DCD 0x10101010
|L1.360|
000168 09090909 DCD 0x09090909
|L1.364|
00016c e59ff018 DCD 0xe59ff018
|L1.368|
000170 00000000 DCD OS_CPU_ARM_ExceptUndefInstrHndlr
|L1.372|
000174 00000000 DCD OS_CPU_ARM_ExceptSwiHndlr
|L1.376|
000178 00000000 DCD OS_CPU_ARM_ExceptPrefetchAbortHndlr
|L1.380|
00017c 00000000 DCD OS_CPU_ARM_ExceptDataAbortHndlr
|L1.384|
000180 00000000 DCD OS_CPU_ARM_ExceptAddrAbortHndlr
|L1.388|
000184 00000000 DCD OS_CPU_ARM_ExceptIrqHndlr
|L1.392|
000188 00000000 DCD OS_CPU_ARM_ExceptFiqHndlr
AREA ||.data||, DATA, ALIGN=1
OSTmrCtr
000000 0000 DCB 0x00,0x00
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