📄 ub.asm
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page 60,132
title UNCOMPRESSED BIOS START CODE
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-1996, American Megatrends Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
;** 6145-F, Northbelt Parkway, Norcross, **;
;** **;
;** Georgia - 30071, USA. Phone-(770)-246-8600. **;
;** **;
;*****************************************************************;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------;
include mbiosequ.equ ; bios global constants
include mbiosmac.mac ; bios coding macro definition
include bblkinit.equ
;---------------------------------------;
public u_bios_suru
public ptr_to_source_buffer
extrn u_power_on_init:near
public u_power_on_init_end
extrn u_cp_init:near
public u_cp_init_end
extrn rom_filename:byte
extrn boot_block_flag:byte
extrn refresh_low_value:byte
extrn bootblock_fdc_table:byte
extrn bootblock_fdc_table_end:byte
extrn bootblock_kbc_rtc_table:byte
extrn bootblock_kbc_rtc_table_end:byte
extrn go_to_flat_mode:near
extrn fixed_delay:near
extrn search_compressed_module:near
extrn ib_free:near
extrn cmos_data_in:near
extrn cmos_data_out:near
extrn restore_cpuid:near
extrn check_ctrl_home:near
extrn check_main_bios_checksum:near
extrn form_rom_image:near
extrn get_start_of_init_code:near
;---------------------------------------;
extrn int_0e:word
extrn diskette_parameter_table:word
extrn int_40:word
extrn init_8237_dma:near
extrn enable_internal_cache:near
extrn disable_internal_cache:near
extrn flash_program:near
extrn display_blink_halt:near
extrn display_on_port:near
extrn floppy_cntlr_err:byte
extrn file_abs_msg:byte
extrn flp_ins_msg:byte
extrn read_err_msg:byte
extrn flp_read_msg:byte
;---------------------------------------;
cgroup group _text
_text segment word public 'CODE'
assume cs:cgroup
.486p
;---------------------------------------;
public _UB_STARTS
_UB_STARTS label byte ; marks start of module
;---------------------------------------;
u_bios_suru:
cli ; test under CLI mode
cld ; ensure direction
mov ax,cs
mov ss,ax
jmp u_power_on_init
u_power_on_init_end:
;---------------------------------------;
; ENABLE RTC, KBC if controlled by;
; on-board I/O chipset.. ;
;---------------------------------------;
mov si,offset cgroup:bootblock_kbc_rtc_table
kbcrtc_00:
cmp si,offset cgroup:bootblock_kbc_rtc_table_end
jae kbcrtc_end
lods cs:word ptr [si] ; AX = routine offset
mov sp,offset cgroup:kbcrtc_01
jmp ax ; do not destroy EDX, SI, SS, SP
even
kbcrtc_01:
dw offset cgroup:kbcrtc_02
kbcrtc_02:
jmp short kbcrtc_00
kbcrtc_end:
;---------------------------------------;
; Disable NMI and PARITY ;
;---------------------------------------;
mov al,0ch
out 61h,al ; disable parity
check_point_ini 0d0h ; ========== D0
mov ebp,edx ; store bit31-16 of EDX in bit31-16 of EBP
;---------------------------------------;
; VERIFY CHECKSUM ;
;---------------------------------------;
ret_sp get_start_of_init_code ; DS:DI = ptr to bios header+1
; DS:DI = ptr to start of init code
mov si,di ; start offset of init code
mov cx,di ; start offset of init code
neg cx ; CX = init code size in bytes
shr cx,3 ; CX = init code size #of qwords
xor eax,eax ; result of checksum
checksum_1:
add eax,cs:[si]
add si,08h
add eax,cs:[si-4]
loop checksum_1
jnz $ ; checksum bad, halt
check_point_ini 0d1h ; ========== D1
;---------------------------------------;
; KEYBOARD CONTROLLER TEST ;
;---------------------------------------;
in al,64h
and al,04h ; sys bit unchanged
mov ah,al ; save sys bit
mov al,0aah ; BAT command AA
out 64h,al
kb_2:
jcxz $+2
in al,64h
test al,1
jz kb_2
in al,60h ; BAT result 55
mov al,60h
out 64h,al ; command byte
kb_3:
jcxz $+2
in al,64h
test al,2
jnz kb_3
mov al,ah
or al,61h ; keyboard enable, mouse disable
out 60h,al
kb_4:
jcxz $+2
in al,64h
test al,2
jnz kb_4
;---------------------------------------;
; Check for Wake Up ;
;---------------------------------------;
; (CORE0071)>
; extrn u_wake_up:near
extern u_wake_up(u_wake_up_end):near
; <(CORE0071)
public u_wake_up_end
jmp u_wake_up
u_wake_up_end:
;---------------------------------------;
; Save CPU-ID in CMOS 35,36 ;
; Verify the data written in CMOS ;
;---------------------------------------;
mov edx,ebp
cmos_not_good_yet:
mov al,0b5h ; access cmos 35h and disable NMI
out 70h,al
io_delay
mov al,dl
out 71h,al
io_delay
mov al,0b5h
out 70h,al
io_delay
in al,71h
io_delay
cmp al,dl
jnz cmos_not_good_yet
mov al,0b6h
out 70h,al
io_delay
mov al,dh
out 71h,al
;---------------------------------------;
; START MEMORY REFRESH ;
;---------------------------------------;
;---------------------------------------;
; CHIPSET REGISTER PROGRAMMING ;
;---------------------------------------;
jmp_si go_to_flat_mode ; DS=ES=0 (4GB limit), GateA20 enabled
check_point_ini 0d3h ; ======== D3
jmp u_cp_init ; init all chipset register
u_cp_init_end:
check_point_ini 0d4h ; ======== D4
;---------------------------------------;
; 512 KB MEMORY TEST ;
;---------------------------------------;
xor ax,ax
mov es,ax
mov bx,es:word ptr [472h] ; save 40:72
mov eax,5aa5a55ah
mov edx,eax
memory_test:
xor edi,edi
mov ecx,4000h*8 ; 512kb memory = 64k*8 dword
db 67h
rep stosd
xor edi,edi
mov ecx,4000h*8 ; 512kb memory = 64k*8 dword
db 67h
repz scasd
jnz $
xor eax,edx
jz memory_test
mov es:word ptr [472h],bx ; restore 40:72
;---------------------------------------;
;;;; jmp_si comeback_from_flat_mode ; DS=ES=0 with 64KB limit
;---------------------------------------;
; COPY 8K CODE TO SEGMENT 0 ;
;---------------------------------------;
check_point_ini 0d5h ; ======== D5
ret_sp get_start_of_init_code ; DS:DI = ptr to bios header+1
; DS:DI = ptr to start of init code
xor ax,ax
mov ds,ax
mov ss,ax
mov sp,di ; SS:SP = 0000:start of init code
; DS = ES = 0 with 4GB access
mov si,di ; start offset of init code
mov cx,di ; start offset of init code
neg cx ; CX = init code size in bytes
shr cx,2 ; CX = init code size #of dwords
rep movs es:dword ptr [di],cs:dword ptr [si]
push es
push offset cgroup:s0_00
retf ; goto 0000:same address
s0_00:
check_point_ini 0d6h ; ======== D6
call check_ctrl_home ; execute this routine from segment 0
pushf
call form_rom_image ; ESI = start address of buffer
; CX = ROM size in 64k unit
popf
jz cmb_03 ; <CTRL><HOME> pressed, goto flash programming
call check_main_bios_checksum; verify BIOS checksum
jnz cmb_03 ; checksum bad, goto flash programming
;---------------------------------------;
; TRANSFER CONTROL TO MAIN BIOS ;
;---------------------------------------;
check_point_ini 0d7h ; ======== D7
; simulate hard reset by programming keyboard controller..
mov al,60h
out 64h,al ; keyboard command byte
call ib_free
mov al,30h ; hard reset, disable kb, mouse
out 60h,al
call ib_free
in al,60h ; consume data if any
;---------------------------------------;
mov bl,bblk_runtime_interface_module_id
call search_compressed_module
jnz $ ; module not found
; AX:BX = seg:off of start of uncompressed module
; DI = module size in bytes
mov cx,di
mov ds,ax
mov si,bx
push ram_segment-2000h
pop es
xor di,di
push es
push di
rep movsb
call restore_cpuid ; restore EDX
; EDX = CPUID at power-on
retf ; goto 1000:0000 to uncompress runtime
; and to give control to runtime
;---------------------------------------;
; MAIN BIOS CHECKSUM BAD or ;
; <CTRL><HOME> pressed.. ;
; go to flash programming.. ;
;---------------------------------------;
cmb_03:
push es
; initialize the IO chipset (if any) for Floppy
mov si,offset cgroup:bootblock_fdc_table
fdc_00:
cmp si,offset cgroup:bootblock_fdc_table_end
jae fdc_end
lods cs:word ptr [si] ; AX = routine offset
call ax ; do not destroy SI
jmp short fdc_00
fdc_end:
pop es ; ES = 0000 with 4GB access
push 0040h
pop ds ; DS = 0040h
;;;; jmp r_memory_0 ; goto flash programming
;---------------------------------------;
;*****************************************************************;
;*****************************************************************;
;** **;
;** (C)Copyright 1985-1996, American Megatrends Inc. **;
;** **;
;** All Rights Reserved. **;
;** **;
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