cpu4.rpt

Verilog HDL编写的4条指令CPU

-- Node name is ':117' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = DFFE( _LC2_A2,  q0,  VCC,  VCC,  VCC);

-- Node name is ':118' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = DFFE( _LC6_A2,  q0,  VCC,  VCC,  VCC);

-- Node name is ':119' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = DFFE( _EQ067,  q0,  VCC,  VCC,  VCC);
  _EQ067 =  _LC6_A1 &  _LC6_A2
         #  _LC2_A2 &  _LC6_A1
         #  _LC4_A1;

-- Node name is ':120' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ068);
  _EQ068 = !irh6 & !irh7 &  _LC4_A1 &  _LC6_A1;

-- Node name is '~159~1' 
-- Equation name is '~159~1', location is LC5_D8, type is buried.
-- synthesized logic cell 
_LC5_D8  = LCELL( _EQ069);
  _EQ069 =  _LC3_D11 &  o_d7
         #  ac7 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~160~1' 
-- Equation name is '~160~1', location is LC8_D11, type is buried.
-- synthesized logic cell 
_LC8_D11 = LCELL( _EQ070);
  _EQ070 =  _LC3_D11 &  o_d6
         #  ac6 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~161~1' 
-- Equation name is '~161~1', location is LC7_D2, type is buried.
-- synthesized logic cell 
_LC7_D2  = LCELL( _EQ071);
  _EQ071 =  _LC3_A1 &  _LC5_D2
         #  ac5 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~162~1' 
-- Equation name is '~162~1', location is LC6_D14, type is buried.
-- synthesized logic cell 
_LC6_D14 = LCELL( _EQ072);
  _EQ072 =  _LC3_A1 &  _LC3_D14
         #  ac4 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~163~1' 
-- Equation name is '~163~1', location is LC8_C8, type is buried.
-- synthesized logic cell 
_LC8_C8  = LCELL( _EQ073);
  _EQ073 =  _LC3_A1 &  _LC7_C8
         #  ac3 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~164~1' 
-- Equation name is '~164~1', location is LC5_C6, type is buried.
-- synthesized logic cell 
_LC5_C6  = LCELL( _EQ074);
  _EQ074 =  _LC3_A1 &  _LC3_C6
         #  ac2 & !_LC3_A1 & !_LC3_D11;

-- Node name is '~165~1' 
-- Equation name is '~165~1', location is LC5_C29, type is buried.
-- synthesized logic cell 
_LC5_C29 = LCELL( _EQ075);
  _EQ075 =  ac1 & !_LC3_A1 & !_LC3_D11
         #  ac1 &  _LC3_A1 & !_LC3_C29
         # !ac1 &  _LC3_A1 &  _LC3_C29;

-- Node name is '~166~1' 
-- Equation name is '~166~1', location is LC4_C29, type is buried.
-- synthesized logic cell 
_LC4_C29 = LCELL( _EQ076);
  _EQ076 =  ac0 & !_LC3_A1 & !_LC3_D11
         # !ac0 &  _LC3_A1 &  tmp0
         #  ac0 &  _LC3_A1 & !tmp0;

-- Node name is ':183' 
-- Equation name is '_LC5_D11', type is buried 
!_LC5_D11 = _LC5_D11~NOT;
_LC5_D11~NOT = LCELL( _EQ077);
  _EQ077 =  irh7
         #  irh6
         # !_LC2_A2;

-- Node name is ':245' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ078);
  _EQ078 = !_LC1_A1 & !_LC6_A1 &  _LC8_A1;

-- Node name is ':302' 
-- Equation name is '_LC3_D11', type is buried 
!_LC3_D11 = _LC3_D11~NOT;
_LC3_D11~NOT = LCELL( _EQ079);
  _EQ079 =  irh7
         # !irh6
         # !_LC2_A2;

-- Node name is ':327' 
-- Equation name is '_LC1_D9', type is buried 
_LC1_D9  = LCELL( _EQ080);
  _EQ080 =  irh6 & !irh7 &  _LC1_D9 &  _LC2_A2
         # !irh6 &  irh7 &  _LC2_A2;

-- Node name is ':339' 
-- Equation name is '_LC5_D17', type is buried 
_LC5_D17 = LCELL( _EQ081);
  _EQ081 =  _LC5_D11
         #  _LC3_D11
         #  _LC6_A2;

-- Node name is ':348' 
-- Equation name is '_LC2_D9', type is buried 
_LC2_D9  = LCELL( _EQ082);
  _EQ082 = !cy_reg &  irh6 &  irh7 &  _LC2_A2;

-- Node name is '~375~1' 
-- Equation name is '~375~1', location is LC4_D17, type is buried.
-- synthesized logic cell 
_LC4_D17 = LCELL( _EQ083);
  _EQ083 = !_LC2_D9 & !_LC6_A2 &  pc_o5
         #  irh5 &  _LC2_D9;

-- Node name is '~376~1' 
-- Equation name is '~376~1', location is LC7_D14, type is buried.
-- synthesized logic cell 
_LC7_D14 = LCELL( _EQ084);
  _EQ084 = !_LC2_D9 & !_LC6_A2 &  pc_o4
         # !_LC1_C35 &  _LC6_A2 &  pc_o4
         #  _LC1_C35 &  _LC6_A2 & !pc_o4;

-- Node name is '~377~1' 
-- Equation name is '~377~1', location is LC8_C35, type is buried.
-- synthesized logic cell 
_LC8_C35 = LCELL( _EQ085);
  _EQ085 =  irh3 &  _LC2_D9
         #  _LC6_A2 &  _LC6_C35;

-- Node name is '~378~1' 
-- Equation name is '~378~1', location is LC7_C6, type is buried.
-- synthesized logic cell 
_LC7_C6  = LCELL( _EQ086);
  _EQ086 =  irh2 &  _LC2_D9
         #  _LC6_A2 &  _LC6_C30;

-- Node name is '~379~1' 
-- Equation name is '~379~1', location is LC7_C30, type is buried.
-- synthesized logic cell 
_LC7_C30 = LCELL( _EQ087);
  _EQ087 = !_LC2_D9 & !_LC6_A2 &  pc_o1
         #  _LC6_A2 & !pc_o0 &  pc_o1
         #  _LC6_A2 &  pc_o0 & !pc_o1;

-- Node name is ':389' 
-- Equation name is '_LC4_D9', type is buried 
_LC4_D9  = LCELL( _EQ088);
  _EQ088 =  _LC6_A2 &  pc_o7;

-- Node name is ':390' 
-- Equation name is '_LC3_D9', type is buried 
_LC3_D9  = LCELL( _EQ089);
  _EQ089 =  _LC6_A2 &  pc_o6;

-- Node name is '~444~1' 
-- Equation name is '~444~1', location is LC6_D9, type is buried.
-- synthesized logic cell 
_LC6_D9  = LCELL( _EQ090);
  _EQ090 = !irh7 &  _LC2_A2
         # !irh6 &  _LC2_A2;

-- Node name is ':444' 
-- Equation name is '_LC3_D17', type is buried 
_LC3_D17 = LCELL( _EQ091);
  _EQ091 =  irh5 &  _LC6_D9
         #  _LC6_A2 &  pc_o5;

-- Node name is ':445' 
-- Equation name is '_LC2_D14', type is buried 
_LC2_D14 = LCELL( _EQ092);
  _EQ092 =  irh4 &  _LC6_D9
         #  _LC6_A2 &  pc_o4;

-- Node name is ':446' 
-- Equation name is '_LC7_C35', type is buried 
_LC7_C35 = LCELL( _EQ093);
  _EQ093 =  irh3 &  _LC6_D9
         #  _LC6_A2 &  pc_o3;

-- Node name is ':447' 
-- Equation name is '_LC4_C6', type is buried 
_LC4_C6  = LCELL( _EQ094);
  _EQ094 =  irh2 &  _LC6_D9
         #  _LC6_A2 &  pc_o2;

-- Node name is ':448' 
-- Equation name is '_LC5_C30', type is buried 
_LC5_C30 = LCELL( _EQ095);
  _EQ095 =  irh1 &  _LC6_D9
         #  _LC6_A2 &  pc_o1;

-- Node name is ':449' 
-- Equation name is '_LC8_C30', type is buried 
_LC8_C30 = LCELL( _EQ096);
  _EQ096 =  irh0 &  _LC6_D9
         #  _LC6_A2 &  pc_o0;



Project Information           d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 32,929K