📄 cpu4.rpt
字号:
65 - - - 09 OUTPUT 0 1 0 0 o_a6
118 - - - 09 OUTPUT 0 1 0 0 o_a7
11 - - C -- TRI 0 1 0 4 o_d0
17 - - C -- TRI 0 1 0 4 o_d1
95 - - C -- TRI 0 1 0 4 o_d2
97 - - C -- TRI 0 1 0 4 o_d3
19 - - D -- TRI 0 1 0 4 o_d4
92 - - D -- TRI 0 1 0 4 o_d5
21 - - D -- TRI 0 1 0 3 o_d6
88 - - D -- TRI 0 1 0 3 o_d7
13 - - C -- OUTPUT 0 1 0 0 pc0
14 - - C -- OUTPUT 0 1 0 0 pc1
114 - - - 06 OUTPUT 0 1 0 0 pc2
28 - - E -- OUTPUT 0 1 0 0 pc3
90 - - D -- OUTPUT 0 1 0 0 pc4
22 - - D -- OUTPUT 0 1 0 0 pc5
20 - - D -- OUTPUT 0 1 0 0 pc6
64 - - - 10 OUTPUT 0 1 0 0 pc7
122 - - - 18 OUTPUT 0 1 0 0 rc
27 - - E -- OUTPUT 0 1 0 0 tp0
44 - - - 29 OUTPUT 0 1 0 0 tp1
18 - - C -- OUTPUT 0 1 0 0 tp2
96 - - C -- OUTPUT 0 1 0 0 tp3
89 - - D -- OUTPUT 0 1 0 0 tp4
73 - - - 01 OUTPUT 0 1 0 0 tp5
23 - - D -- OUTPUT 0 1 0 0 tp6
117 - - - 08 OUTPUT 0 1 0 0 tp7
100 - - A -- OUTPUT 0 1 0 0 t0
102 - - A -- OUTPUT 0 1 0 0 t1
101 - - A -- OUTPUT 0 1 0 0 t2
82 - - F -- OUTPUT 0 1 0 0 wc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt
cpu4
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 29 OR2 0 4 0 2 |lpm_add_sub:492|addcore:adder|pcarry1
- 5 - C 08 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|pcarry2
- 2 - C 08 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|pcarry3
- 4 - D 02 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|pcarry4
- 8 - D 02 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|pcarry5
- 3 - D 08 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|pcarry6
- 7 - D 08 OR2 0 3 0 1 |lpm_add_sub:492|addcore:adder|pcarry7
- 3 - C 29 OR2 s 0 3 0 1 |lpm_add_sub:492|addcore:adder|~115~1
- 3 - C 06 OR2 0 3 0 1 |lpm_add_sub:492|addcore:adder|:116
- 7 - C 08 OR2 0 3 0 1 |lpm_add_sub:492|addcore:adder|:117
- 3 - D 14 OR2 0 3 0 1 |lpm_add_sub:492|addcore:adder|:118
- 5 - D 02 OR2 0 3 0 1 |lpm_add_sub:492|addcore:adder|:119
- 2 - D 11 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|:120
- 4 - D 08 OR2 0 3 0 2 |lpm_add_sub:492|addcore:adder|:121
- 1 - C 35 AND2 0 4 0 4 |lpm_add_sub:493|addcore:adder|:129
- 1 - D 17 AND2 0 2 0 1 |lpm_add_sub:493|addcore:adder|:133
- 7 - D 17 AND2 0 3 0 1 |lpm_add_sub:493|addcore:adder|:137
- 7 - D 09 AND2 0 4 0 1 |lpm_add_sub:493|addcore:adder|:141
- 6 - C 30 OR2 0 3 0 1 |lpm_add_sub:493|addcore:adder|:150
- 6 - C 35 OR2 0 4 0 1 |lpm_add_sub:493|addcore:adder|:151
- 1 - B 06 SOFT s ! 1 0 0 33 reset~1
- 5 - A 01 DFFE + 1 1 0 1 q2 (:77)
- 2 - A 01 DFFE + 1 1 1 43 q1 (:78)
- 7 - A 01 DFFE + 1 2 0 4 q0 (:79)
- 2 - A 02 OR2 ! 0 3 0 7 :86
- 4 - A 01 AND2 s 0 2 0 2 ~100~1
- 6 - A 01 DFFE 0 2 1 4 :117
- 1 - A 01 DFFE 0 2 1 3 :118
- 8 - A 01 DFFE 0 5 1 3 :119
- 3 - A 01 AND2 0 4 0 13 :120
- 5 - D 08 OR2 s 0 4 0 2 ~159~1
- 8 - D 11 OR2 s 0 4 0 2 ~160~1
- 7 - D 02 OR2 s 0 4 0 2 ~161~1
- 6 - D 14 OR2 s 0 4 0 2 ~162~1
- 8 - C 08 OR2 s 0 4 0 2 ~163~1
- 5 - C 06 OR2 s 0 4 0 2 ~164~1
- 5 - C 29 OR2 s 0 4 0 2 ~165~1
- 4 - C 29 OR2 s 0 4 0 2 ~166~1
- 6 - D 08 DFFE s 0 5 1 0 ac7~1 (~167~1)
- 8 - D 08 DFFE 0 5 1 3 ac7 (:167)
- 6 - D 11 DFFE s 0 5 1 0 ac6~1 (~168~1)
- 4 - D 11 DFFE 0 5 1 3 ac6 (:168)
- 2 - D 02 DFFE s 0 5 1 0 ac5~1 (~169~1)
- 1 - D 02 DFFE 0 5 1 3 ac5 (:169)
- 4 - D 14 DFFE s 0 5 1 0 ac4~1 (~170~1)
- 1 - D 14 DFFE 0 5 1 3 ac4 (:170)
- 3 - C 08 DFFE s 0 5 1 0 ac3~1 (~171~1)
- 1 - C 08 DFFE 0 5 1 3 ac3 (:171)
- 6 - C 06 DFFE s 0 5 1 0 ac2~1 (~172~1)
- 8 - C 06 DFFE 0 5 1 3 ac2 (:172)
- 7 - C 29 DFFE s 0 5 1 0 ac1~1 (~173~1)
- 6 - C 29 DFFE 0 5 1 2 ac1 (:173)
- 2 - C 35 DFFE s 0 5 1 0 ac0~1 (~174~1)
- 1 - C 29 DFFE 0 5 1 3 ac0 (:174)
- 5 - D 11 OR2 ! 0 3 0 9 :183
- 1 - D 08 DFFE 0 4 1 2 tmp7 (:214)
- 7 - D 11 DFFE 0 4 1 2 tmp6 (:215)
- 3 - D 02 DFFE 0 4 1 2 tmp5 (:216)
- 6 - D 02 DFFE 0 4 1 2 tmp4 (:217)
- 4 - C 08 DFFE 0 4 1 2 tmp3 (:218)
- 6 - C 08 DFFE 0 4 1 2 tmp2 (:219)
- 2 - C 29 DFFE 0 4 1 2 tmp1 (:220)
- 3 - C 35 DFFE 0 4 1 3 tmp0 (:221)
- 2 - D 08 DFFE 0 4 1 1 cy_reg (:243)
- 6 - A 02 AND2 0 3 0 30 :245
- 8 - D 09 DFFE 0 4 1 6 irh7 (:274)
- 1 - D 11 DFFE 0 4 1 6 irh6 (:275)
- 8 - D 17 DFFE 0 4 1 2 irh5 (:276)
- 8 - D 14 DFFE 0 4 1 2 irh4 (:277)
- 4 - C 35 DFFE 0 4 1 2 irh3 (:278)
- 2 - C 06 DFFE 0 4 1 2 irh2 (:279)
- 1 - C 30 DFFE 0 4 1 2 irh1 (:280)
- 3 - C 30 DFFE 0 4 1 2 irh0 (:281)
- 3 - D 11 OR2 ! 0 3 0 21 :302
- 1 - D 09 OR2 0 3 1 0 :327
- 5 - D 17 OR2 0 3 1 0 :339
- 2 - D 09 AND2 0 4 0 12 :348
- 4 - D 17 OR2 s 0 4 0 1 ~375~1
- 7 - D 14 OR2 s 0 4 0 1 ~376~1
- 8 - C 35 OR2 s 0 4 0 1 ~377~1
- 7 - C 06 OR2 s 0 4 0 1 ~378~1
- 7 - C 30 OR2 s 0 4 0 1 ~379~1
- 5 - D 09 DFFE 0 4 1 1 pc_o7 (:381)
- 2 - D 17 DFFE 0 4 1 2 pc_o6 (:382)
- 6 - D 17 DFFE 0 4 1 4 pc_o5 (:383)
- 5 - D 14 DFFE 0 4 1 5 pc_o4 (:384)
- 5 - C 35 DFFE 0 4 1 3 pc_o3 (:385)
- 1 - C 06 DFFE 0 4 1 4 pc_o2 (:386)
- 4 - C 30 DFFE 0 4 1 5 pc_o1 (:387)
- 2 - C 30 DFFE 0 4 1 5 pc_o0 (:388)
- 4 - D 09 AND2 0 2 1 0 :389
- 3 - D 09 AND2 0 2 1 0 :390
- 6 - D 09 OR2 s 0 3 0 6 ~444~1
- 3 - D 17 OR2 0 4 1 0 :444
- 2 - D 14 OR2 0 4 1 0 :445
- 7 - C 35 OR2 0 4 1 0 :446
- 4 - C 06 OR2 0 4 1 0 :447
- 5 - C 30 OR2 0 4 1 0 :448
- 8 - C 30 OR2 0 4 1 0 :449
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt
cpu4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/144( 2%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 19/144( 13%) 3/ 72( 4%) 5/ 72( 6%) 0/16( 0%) 5/16( 31%) 4/16( 25%)
D: 22/144( 15%) 9/ 72( 12%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 4/16( 25%)
E: 0/144( 0%) 2/ 72( 2%) 3/ 72( 4%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
F: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
09: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
30: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt
cpu4
** CLOCK SIGNALS **
Type Fan-out Name
DFF 44 q1
DFF 5 q0
INPUT 3 clk
Device-Specific Information: d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt
cpu4
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 12 reset
Device-Specific Information: d:\documents\studio\exp\part 2\1-in_clk\cpu4.rpt
cpu4
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is 'acc0'
-- Equation name is 'acc0', type is output
acc0 = _LC2_C35;
-- Node name is 'acc1'
-- Equation name is 'acc1', type is output
acc1 = _LC7_C29;
-- Node name is 'acc2'
-- Equation name is 'acc2', type is output
acc2 = _LC6_C6;
-- Node name is 'acc3'
-- Equation name is 'acc3', type is output
acc3 = _LC3_C8;
-- Node name is 'acc4'
-- Equation name is 'acc4', type is output
acc4 = _LC4_D14;
-- Node name is 'acc5'
-- Equation name is 'acc5', type is output
acc5 = _LC2_D2;
-- Node name is 'acc6'
-- Equation name is 'acc6', type is output
acc6 = _LC6_D11;
-- Node name is 'acc7'
-- Equation name is 'acc7', type is output
acc7 = _LC6_D8;
-- Node name is '~174~1' = 'ac0~1'
-- Equation name is '~174~1', location is LC2_C35, type is buried.
-- synthesized logic cell
_LC2_C35 = DFFE( _EQ001, q1, VCC, VCC, !_LC1_B6);
_EQ001 = _LC3_D11 & o_d0
# _LC4_C29;
-- Node name is ':174' = 'ac0'
-- Equation name is 'ac0', location is LC1_C29, type is buried.
ac0 = DFFE( _EQ002, q1, VCC, VCC, !_LC1_B6);
_EQ002 = _LC3_D11 & o_d0
# _LC4_C29;
-- Node name is '~173~1' = 'ac1~1'
-- Equation name is '~173~1', location is LC7_C29, type is buried.
-- synthesized logic cell
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