cpu4vec0.vec

Verilog HDL编写的4条指令CPU

%
if OUTPUTS(or BURIED) ==> INPUTS, then deleted "="
if INPUTS ==> OUTPUTS(or BURIED), then PATTERN as follows:

  such as t of text:
RADIX HEX;
GROUP CREATE t = t2 t1 t0;
OUTPUTS t;   
PATTERN  
0>  =0 ;

START 150 ;
STOP 6000 ;
RADIX HEX;
INTERVAL 150 ;
GROUP CREATE t = t2 t1 t0;
OUTPUTS t;  
PATTERN
=1 
=2 
=4;       
%

START 0 ;
STOP 12000 ;
INPUTS reset;
PATTERN
0>   1
50>  0;

START 0 ;
STOP 12000 ;
INPUTS run;
PATTERN
0>    0
100>  1;

%STOP 2400 ;
INPUTS pc_cp;
PATTERN
0>    0
100>  1
150>  0;%

START 0 ;
STOP 150 ;
INPUTS clk ;
PATTERN
0> 0;

START 150 ;
STOP 12000 ;
INTERVAL 50 ;
INPUTS   clk ;
PATTERN
1 0;

RADIX HEX;
START 0 ;
STOP 150 ;
GROUP CREATE q = q2 q1 q0;
BURIED Q ;  %OUTPUTS%
PATTERN
0> = 0 ;

RADIX HEX;
START 150 ;
STOP 12000 ;
INTERVAL 100 ;
BURIED  q;    %OUTPUTS%
PATTERN
 = 1 
 = 2
 = 4;

START 0 ;
STOP 150 ;
INPUTS ck ;
PATTERN
0> 0;

START 150 ;
STOP 12000 ;
INTERVAL 100 ;
INPUTS   ck ;
PATTERN
0 1 0; 


RADIX HEX;
STOP 150;
GROUP CREATE t = t2 t1 t0;
INPUTS t;   
PATTERN  
0>    0 ;


START 150 ;
STOP 12000 ;
RADIX HEX;
INTERVAL 300 ;
% GROUP CREATE t = t2 t1 t0;%
INPUTS t;   
PATTERN
1 2 4;

 
RADIX HEX;
GROUP CREATE o_d = o_d7 o_d6 o_d5 o_d4 o_d3 o_d2 o_d1 o_d0;
INPUTS   o_d;   
PATTERN      % if delay of read  = 30ns %
0>       ZZ   
50>      ZZ
100>     ZZ
180>     4C   
480>     F0
780>     ZZ
1080>    0D
1380>    87
1680>    ZZ
1980>    90
2280>    ZZ
2580>    ZZ
2880>    4E
3180>    42
3480>    ZZ
3780>    C6
4080>    ZZ
4380>    ZZ
4680>    0B
4980>    01
5280>    ZZ
5580>    0F
5880>    51
6180>    ZZ
6480>    91
6780>    ZZ
7080>    ZZ
7380>    0A
7680>    00
7980>    ZZ
8280>    D2
8580>    ZZ
8880>    ZZ
9180>    50
9480>    77
9780>    ZZ
10080>   51
10380>   94  
10680>   ZZ
10980>   D4
11280>   ZZ
11580>   ZZ;


RADIX HEX;
%GROUP CREATE o_d = o_d7 o_d6 o_d5 o_d4 o_d3 o_d2 o_d1 o_d0;%
GROUP CREATE o_a = o_a7 o_a6 o_a5 o_a4 o_a3 o_a2 o_a1 o_a0;
GROUP CREATE i_reg = i_reg7 i_reg6 i_reg5 i_reg4 i_reg3 i_reg2 i_reg1 i_reg0;
GROUP CREATE ac = ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0;
GROUP CREATE tp = tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0;
GROUP CREATE pc = pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0;
OUTPUTS o_d o_a i_reg ac tp pc;
PATTERN
0>   = ZZ 00 00 00 00 00;
 

RADIX HEX;
OUTPUTS wc rc cy;
PATTERN
0>    = 0  0  0;