cpu4.v

Verilog HDL编写的4条指令CPU

/* Verilog HDL    
  design of CPU--4 item instruction, 8 bit 
  control mode---combination logic        
  IRH[7..0]------Instruction Register High 8bit)
  irh[7], irh[6]-----2 bit operation code
  IRH[5..0]------6 bit address 
  A_d[7..0]------accumulator register
  irh[7] irh[6]  instruction     operation
    0    0   ADD A_d, addr   A_d  <= (A_d) + (addr)
    0    1   LDA A_d, addr   A_d  <= (addr) 
    1    0   STA add, A_d    addr <= (A_d) 
    1    1   JNC addr        pc   <= addr, when Cy=0
  Cy-------------Carry of Adder
  PC_i[7..0]-------program counter
  T[2..0]--------3 cycle
  CK-------------in cycle, contain clock        
文件有7处错误，请查出___已改正！*/

module cpu4( reset, clk, wc, rc, o_d, o_a, pc, //  ,pc_cp,run
                    i_reg, acc, cy, ck,tp ,t);
            //stop, end_i, CK_10K, ,addr, fb_d);

  input        clk, reset; 		//run;
  output       wc;            	//CPU write order (need pulse) 
  output       rc;            	//CPU read  order 
  inout[7:0]   o_d;           	//outside data bus
  output[7:0]  o_a;           	//outside address bus
  output[7:0]  pc;
  output	   ck;
  output[2:0]  t;
  //input        pc_cp;         //clock of PC machine setup cpu_pc
  
  
  //When simulator,look at inside information  to need *******************
  output[7:0] 	i_reg;
  output[7:0]	acc;
  output[7:0] 	tp;
  output       	cy;
    
  //When online test, cpu experiment system  need ************************
  //output       stop;          //STOP Machine
  //output       end_i;         //end of One_order
  //input        CK_10K;
  //when test,look at CPU'S information in screen
  //input[4:0]   addr;          //address of feedback information
  //output[7:0]  fb_d;          //information of feedback

  //时序的变化
	reg		[2:0]	t;
	reg		[2:0]	q;

  	always @ (posedge clk ) 
		begin
			if(reset==0)
				begin
					q[0]<=(~q[2]&~q[1]&~q[0])|q[2];
					q[1]<=q[0];
					q[2]<=q[1];
				end
			else
					q<=3'b000;
		end

	assign	ck=q[1];
	wire	x=q[0];	

	always @ (posedge x)
		begin
			if(t==3'b100||t==3'b010||t==3'b001||t==3'b000)
				begin
					t[0]<=(~t[2]&~t[1]&~t[0])|t[2];
					t[1]<=t[0];
					t[2]<=t[1];
				end
			else
					t<=3'b000;
		end

	
 
  reg[7:0]     i_a;            //inside address bus
  reg[7:0]     i_d;            //inside data bus
      
  reg          rc;
  reg          wc;
 
  reg[7:0]     ac;           //Acc_Reg   
  reg[7:0]     tmp;           //temp REG in_B of ALU
                      
  reg[7:0]     irh;           //instruction_Reg 
  reg[7:0]     pc_o;          //CPU program counter wich load (OUT)

  reg          cy_reg;        //carry_Reg 
                 
  //reg[7:0]     qq;            //feedcall cpu's information all out

  //high level ****************************************************

 assign  acc=ac;     
 assign  tp=tmp;
 assign  i_reg=irh; 
 assign  pc=pc_o;
 assign  cy=cy_reg;

 always @( irh[7:0] or t 
         or pc_o or tmp or cy_reg or ac )                           
   begin
     casex ({irh[7:6],t,cy_reg})
        6'bxx001x:           //t0:fetch instruction
          begin
            i_a = pc_o;
            rc  = 1'b1;
            wc  = 1'b0;
          end
        6'b00010x:          // t1:ADD fetch data      
          begin
            i_a = {2'b00,irh[5:0]};
            rc  = 1'b1;
            wc  = 1'b0;
          end
        6'b01010x:          // t1:LDA fetch data  
          begin
            i_a = {2'b00,irh[5:0]};
            rc  = 1'b1;
           
          end
        6'b10010x:          // t1:STA write data  
          begin
            i_a = {2'b00,irh[5:0]};
            wc  = 1'b1;
            rc  = 1'b0;
            i_d = ac;
          end      
        6'bxx000x:          // no work  
          begin
            i_a = 8'h00;
            wc    = 1'b0;
            rc    = 1'b0;
          end  
        default:
          begin
            i_a = 8'h00;
            i_d = 8'hxx;
            wc  = 1'b0;
            rc  = 1'b0;
          end    
     endcase 
   end
   
   
 always @( posedge ck or posedge reset)
                                    
   begin
      if (reset)
      pc_o <= 8'h00;
      else
     casex ({irh[7:6],t,cy_reg})
        6'bxx001x:           //t0:fetch instruction
          begin
            irh <= o_d;
            pc_o<= pc_o + 1; 
          end
        6'b00010x:          // t1:ADD fetch data      
          begin
            tmp <= o_d;
          end
        6'b00100x:          // t2:add +  
          begin
            {cy_reg,ac} <= {1'b0,ac} + {1'b0,tmp};
          end
        6'b01010x:          // t1:LDA fetch data  
          begin
            ac <= o_d;
          end
        6'b110100:          // t1:JNC  
          begin
            pc_o <= {2'b00,irh[5:0]};
          end   
     endcase 
   end

  assign o_a = i_a;

          
  \74465 o_d_bus(.gn({~wc,1'b0}),.a(ac),.y(o_d));  //STA  write  memory
      
    
endmodule