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SOPC_Builder_Version = "0.0";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER addr_bits
{
parameter_name = "ADDR_BITS";
type = "integer";
default_value = "18";
editable = "1";
tooltip = "";
}
HDL_PARAMETER data_bits
{
parameter_name = "DATA_BITS";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER addr_low
{
parameter_name = "ADDR_LOW";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
HDL_PARAMETER byte_en_bits
{
parameter_name = "BYTE_EN_BITS";
type = "integer";
default_value = "2";
editable = "1";
tooltip = "";
}
}
}
}
}
}
FILE Altera_UP_Avalon_to_External_Bus_Bridge.vhd
{
file_mod = "Wed Sep 20 10:49:41 EDT 2006";
quartus_map_start = "Wed Sep 20 10:49:41 EDT 2006";
quartus_map_finished = "Wed Sep 20 10:49:53 EDT 2006";
#found 1 valid modules
WRAPPER altera_up_avalon_to_external_bus_bridge
{
CLASS altera_up_avalon_to_external_bus_bridge
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "D:/MyWork/IP/InProgress/altera_up_avalon_to_external_bus_bridge/hdl/Altera_UP_Avalon_to_External_Bus_Bridge.vhd";
}
}
top_module_name = "altera_up_avalon_to_external_bus_bridge";
emit_system_h = "0";
LIBRARIES
{
library = "ieee.std_logic_1164.all";
library = "ieee.std_logic_unsigned.all";
library = "std.standard.all";
}
}
MODULE_DEFAULTS global_signals
{
class = "altera_up_avalon_to_external_bus_bridge";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT avalon_address
{
width = "-1";
width_expression = "((addr_bits - 1)) - (0) + 1";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_byteenable
{
width = "-1";
width_expression = "((byte_en_bits - 1)) - (0) + 1";
direction = "input";
type = "byteenable";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_chipselect
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_read
{
width = "1";
width_expression = "";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_write
{
width = "1";
width_expression = "";
direction = "input";
type = "write";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_writedata
{
width = "-1";
width_expression = "((data_bits - 1)) - (0) + 1";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_readdata
{
width = "-1";
width_expression = "((data_bits - 1)) - (0) + 1";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_waitrequest
{
width = "1";
width_expression = "";
direction = "output";
type = "waitrequest";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT acknowledge
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT address
{
width = "32";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT bus_enable
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT byte_enable
{
width = "-1";
width_expression = "((byte_en_bits - 1)) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rw
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT write_data
{
width = "-1";
width_expression = "((data_bits - 1)) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
SLAVE data
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT read_data
{
width = "-1";
width_expression = "((data_bits - 1)) - (0) + 1";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT reset
{
width = "1";
width_expression = "";
direction = "input";
type = "reset";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "altera_up_avalon_to_external_bus_bridge";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER addr_bits
{
parameter_name = "addr_bits";
type = "integer";
default_value = "18";
editable = "1";
tooltip = "";
}
HDL_PARAMETER data_bits
{
parameter_name = "data_bits";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER addr_low
{
parameter_name = "addr_low";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
HDL_PARAMETER byte_en_bits
{
parameter_name = "byte_en_bits";
type = "integer";
default_value = "2";
editable = "1";
tooltip = "";
}
}
}
}
}
}
}
}
ASSOCIATED_FILES
{
Add_Program = "the_wizard_ui";
Edit_Program = "the_wizard_ui";
Generator_Program = "cb_generator.pl";
}
}
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