📄 class.ptf
字号:
{
layout = "grid";
title = "Size";
spacing = 10;
rows = 2;
columns = 3;
TEXT
{
align="right";
title = "Data Width:";
}
COMBO
{
align="right";
id = "width";
columns = "6";
values = "128,64,32,16,8";
DATA
{
$H/data_bits = "$";
}
}
TEXT
{
align = "left";
title = "bits";
}
TEXT
{
align = "right";
title = "Address Range:";
}
COMBO
{
align="right";
id = "size";
columns = "6";
justify = "right";
values = "1024,512,256,128,64,32,16,8,4,2,1";
DATA
{
$WSA/Size_Value = "$";
}
}
COMBO
{
glue = 0;
align = "left";
id = "units";
ITEM { title="Mbytes"; DATA { $WSA/Size_Multiple = 1048576; }}
ITEM { title="Kbytes"; DATA { $WSA/Size_Multiple = 1024; }}
ITEM { title="bytes"; DATA { $WSA/Size_Multiple = 1; }}
}
}
}
}
}
SOPC_Builder_Version = "6.00";
COMPONENT_BUILDER
{
HDL_PARAMETERS
{
# generated by CBDocument.getParameterContainer
# used only by Component Editor
HDL_PARAMETER addr_bits
{
parameter_name = "ADDR_BITS";
type = "integer";
default_value = "18";
editable = "1";
tooltip = "";
}
HDL_PARAMETER data_bits
{
parameter_name = "DATA_BITS";
type = "integer";
default_value = "16";
editable = "1";
tooltip = "";
}
HDL_PARAMETER addr_low
{
parameter_name = "ADDR_LOW";
type = "integer";
default_value = "1";
editable = "1";
tooltip = "";
}
HDL_PARAMETER byte_en_bits
{
parameter_name = "BYTE_EN_BITS";
type = "integer";
default_value = "2";
editable = "1";
tooltip = "";
}
}
SW_FILES
{
}
built_on = "2006.09.20.10:51:54";
CACHED_HDL_INFO
{
# cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
# used only by Component Builder
FILE Altera_UP_Avalon_to_External_Bus_Bridge.v
{
file_mod = "Wed Sep 20 10:41:52 EDT 2006";
quartus_map_start = "Wed Sep 20 10:48:35 EDT 2006";
quartus_map_finished = "Wed Sep 20 10:48:48 EDT 2006";
#found 1 valid modules
WRAPPER Altera_UP_Avalon_to_External_Bus_Bridge
{
CLASS Altera_UP_Avalon_to_External_Bus_Bridge
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "";
filepath = "D:/MyWork/IP/InProgress/altera_up_avalon_to_external_bus_bridge/hdl/Altera_UP_Avalon_to_External_Bus_Bridge.v";
}
}
top_module_name = "Altera_UP_Avalon_to_External_Bus_Bridge";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "Altera_UP_Avalon_to_External_Bus_Bridge";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT avalon_address
{
width = "-1";
width_expression = "((ADDR_BITS - 1)) - (0) + 1";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_byteenable
{
width = "-1";
width_expression = "((BYTE_EN_BITS - 1)) - (0) + 1";
direction = "input";
type = "byteenable";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_chipselect
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_read
{
width = "1";
width_expression = "";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_write
{
width = "1";
width_expression = "";
direction = "input";
type = "write";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_writedata
{
width = "-1";
width_expression = "((DATA_BITS - 1)) - (0) + 1";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_readdata
{
width = "-1";
width_expression = "((DATA_BITS - 1)) - (0) + 1";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT avalon_waitrequest
{
width = "1";
width_expression = "";
direction = "output";
type = "waitrequest";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT acknowledge
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT address
{
width = "32";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT bus_enable
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT byte_enable
{
width = "-1";
width_expression = "((BYTE_EN_BITS - 1)) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rw
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT write_data
{
width = "-1";
width_expression = "((DATA_BITS - 1)) - (0) + 1";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
SLAVE data
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT read_data
{
width = "-1";
width_expression = "((DATA_BITS - 1)) - (0) + 1";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT reset
{
width = "1";
width_expression = "";
direction = "input";
type = "reset";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "Altera_UP_Avalon_to_External_Bus_Bridge";
technology = "imported components";
}
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -