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## DE2_pio#CLASS altera_up_avalon_DE2_pio{ SDK_GENERATION { SDK_FILES 1 { cpu_architecture = "nios"; c_structure_type = "np_DE2_pio *"; short_type = "DE2_pio"; c_header_file = "sdk/DE2_pio_struct.h"; asm_header_file = "sdk/DE2_pio_struct.s"; sdk_files_dir = "sdk"; } SDK_FILES 2 { cpu_architecture = "else"; toolchain = "gnu"; asm_header_file = "sdk/DE2_pio_struct.s"; } } ASSOCIATED_FILES { Add_Program = "add_edit_ui"; Edit_Program = "add_edit_ui"; Generator_Program = "em_DE2_pio.pl"; } MODULE_DEFAULTS { class = "altera_up_avalon_DE2_pio"; class_version = "6.0"; HDL_INFO { # The list of files associated with this module (for synthesis # and other purposes) depends on the users' wizard-choices. # This section will be filled-in by the Generator_Program # after the module logic has been created and the # various filenames are known. } PORT_WIRING { # The number and kind of ports that appear on this module # depends on the user's wizard-choices. # This section will be filled-in by the Generator_Program # after the module logic has been created and the ports are known. # # The top-level ports must be listed here so that # the SOPC Builder pin assigner knows about them. # The UI may enable some combination of these ports, which # allows pin assignments to be made for the enabled ones. PORT in_port { direction = "input"; Is_Enabled = "0"; width = "4"; } PORT out_port { direction = "output"; Is_Enabled = "0"; width = "4"; } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "4"; } } SLAVE s1 { PORT_WIRING { # The number and kind of ports that appear on this module # depends on the user's wizard-choices. # This section will be filled-in by the Generator_Program # after the module logic has been created and the ports are known. # } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; IRQ_Number = "N/A"; Address_Width = "2"; Data_Width = "8"; Base_Address = "--unknown--"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "1"; has_in = "0"; capture = "0"; edge_type = "NONE"; irq_type = "NONE"; } } USER_INTERFACE { USER_LABELS { name = "DE2 PIO (Parallel I/O)"; technology = "University Program DE1 Board,University Program DE2 Board"; } # LINKS # { # LINK help # { # title = "Data Sheet"; # url = "http://www.altera.com/literature/hb/nios2/n2cpu_nii51007.pdf"; # } # } WIZARD_UI add_edit_ui { title = "UP DE2 Avalon PIO - {{ $MOD }}"; ACTION wizard_finish { $WSA/edge_type = "{{ if ($WSA/capture && ($WSA/has_in || $WSA/has_tri)) $WSA/edge_type; else 'NONE' }}"; $WSA/irq_type = "{{ if ($SBI/Has_IRQ) $WSA/irq_type; else 'NONE' }}"; $MOD/SYSTEM_BUILDER_INFO/View/Settings_Summary = " {{ $SBI/Data_Width }}-bit PIO using <br> {{ if ($WSA/has_tri) ' tri-state pins with edge type '+$WSA/edge_type+' and interrupt source '+$WSA/irq_type }} {{ if ($WSA/has_in) ' input pins with edge type '+$WSA/edge_type+' and interrupt source '+$WSA/irq_type }} {{ if ($WSA/has_out) ' output pins' }}"; # Enable the appropriate ports for use by the pin assigner. $MOD/PORT_WIRING/PORT in_port/Is_Enabled = "{{ $WSA/has_in }}"; $MOD/PORT_WIRING/PORT out_port/Is_Enabled = "{{ $WSA/has_out }}"; $MOD/PORT_WIRING/PORT bidir_port/Is_Enabled = "{{ $WSA/has_tri }}"; $MOD/PORT_WIRING/PORT in_port/width = "{{ $SBI/Data_Width }}"; $MOD/PORT_WIRING/PORT out_port/width = "{{ $SBI/Data_Width }}"; $MOD/PORT_WIRING/PORT bidir_port/width = "{{ $SBI/Data_Width }}"; # set whether this PIO is readable, writable, or both $MOD/SLAVE s1/SYSTEM_BUILDER_INFO/Is_Readable = "{{ ($WSA/has_in || $WSA/has_tri) }}"; $MOD/SLAVE s1/SYSTEM_BUILDER_INFO/Is_Writable = "{{ ($WSA/has_out || $WSA/has_tri) }}"; } PAGES main { select = "1"; PAGE 1 { title = "Basic Settings"; GROUP { title = "Width"; # spacing=8; glue = "0"; EDIT { id = "width"; width = "25"; glue = "0"; key = "w"; suffix = "bits"; type = "decimal"; DATA { $SBI/Data_Width = "$"; } $$bad_width = "{{ $SBI/Data_Width > 32 || $SBI/Data_Width < 1; }}"; error = "{{ if ($$bad_width) 'Invalid PIO width.'; }}"; } TEXT { title = "PIO width must be between 1 and 32 bits"; foreground = "{{ if ($$bad_width) 'red'; else 'black'; }}"; } } GROUP mode { align = "left"; title = "Direction"; spacing = "5"; RADIO { id = "bidir"; title = "Bidirectional (tri-state) ports"; key = "T"; tooltip = "Tri-state ports must be connected <> to device pins."; DATA { has_tri = "1"; has_out = "0"; has_in = "0"; } } RADIO { id = "input"; title = "Input ports only"; key = "I"; DATA { has_tri = "0"; has_out = "0"; has_in = "1"; } } RADIO { id = "inout"; title = "Both input and output ports"; key = "B"; tooltip = "Software can read data from the input port <br>and write data to the separate output port."; DATA { has_tri = "0"; has_out = "1"; has_in = "1"; } } RADIO { id = "output"; title = "Output ports only"; key = "O"; DATA { has_tri = "0"; has_out = "1"; has_in = "0"; $SBI/Has_IRQ = "0"; } } } } PAGE 2 { title = "Input Options"; # this page only enabled if we have inputs. enable = "{{ ($WSA/has_tri==1 || $WSA/has_in==1); }}"; GROUP edge { align = "left"; title = "Edge Capture Register"; CHECK { id = "capture"; title = "Synchronously capture:"; key = "S"; DATA { $WSA/capture = "$"; } ACTION initialize { $$dummy = "{{ if ($WSA/edge_type == 'NONE') {$WSA/capture='0'} else {$WSA/capture='1'}; }}"; } ACTION select { code = "{{ if ($WSA/capture == 0) { $WSA/edge_type = 'NONE'; if ($SBI/Has_IRQ) $WSA/irq_type = 'LEVEL'; } else {$WSA/edge_type = 'RISING'}; }}"; } GROUP edge_type { indent = "20"; RADIO { id = "rising"; title = "Rising Edge"; key = "R"; tooltip = "A rising edge on any input bit sets the <br> corresponding bit in the edge capture register"; DATA { $WSA/edge_type = "RISING"; } } RADIO { id = "falling"; title = "Falling Edge"; key = "a"; tooltip = "A falling edge on any input bit sets the <br> corresponding bit in the edge capture register"; DATA { $WSA/edge_type = "FALLING"; } } RADIO { id = "either"; title = "Either Edge"; key = "E"; tooltip = "A rising or falling edge on any input bit sets the <br> corresponding bit in the edge capture register"; DATA { $WSA/edge_type = "ANY"; } } } } } GROUP irq_settings { title = "Interrupt"; align = "left"; CHECK { title = "Generate IRQ"; id = "irq"; key = "G"; DATA { $SBI/Has_IRQ = "$"; } ACTION select { $$dummy = "{{ if { $SBI/Has_IRQ == 1 && $WSA/irq_type == 'NONE' } $WSA/irq_type = 'LEVEL'; }}"; } GROUP irq_type { indent = "20"; RADIO { title = "Level."; id = "level"; key = "L"; DATA { $WSA/irq_type = "LEVEL"; } GROUP { indent = "40"; TEXT { title = "Interrupt CPU when any unmasked I/O"; } TEXT { title = "pin is logic-true."; } } } RADIO { title = "Edge."; id = "edge"; key = "d"; DATA { $WSA/irq_type = "EDGE"; } enable = "{{ $WSA/capture }}"; GROUP { indent = "40"; TEXT { title = "Interrupt CPU when any unmasked bit in"; } TEXT { title = "the edge-capture register is logic-true."; } } } } } } } PAGE 3 { title = "Simulation"; # this page only enabled if we have inputs. enable = "{{ ($WSA/has_tri==1 || $WSA/has_in==1); }}"; GROUP { title = "Test Bench Wiring"; align = "left"; CHECK { spacing = "5"; title = "Hardwire PIO inputs in test bench"; key = "h"; DATA { $WSA/Do_Test_Bench_Wiring = "$"; } GROUP { indent = "40"; EDIT { align = "left"; width = "50"; glue = "1"; enable = "{{ ($WSA/Do_Test_Bench_Wiring); }}"; key = "V"; type = "hex"; title = "Drive inputs to "; DATA { $WSA/Driven_Sim_Value = $; } $$bad_value = "{{ ($WSA/Driven_Sim_Value >= (2 ^ $SBI/Data_Width)); }}"; error = "{{ if ($$bad_value) 'Value too big for PIO Data Width'; }}"; } } } } } } } }}
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