📄 den_lcm_test.v
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// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions: DEN 3'6 LCD Moudule Test
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 07/06/20 :| Initial Revision
// --------------------------------------------------------------------
module DEN_LCM_TEST
(
//////////////////////// Clock Input ////////////////////////
iCLK_50,
//////////////////////// Push Button ////////////////////////
iKEY,
//////////////////////////// LED ////////////////////////////
oLED,
//////////////////////////// 3.6' LCM Interface ////////////////////////////
oLCM_DATA,
oLCM_GRST,
oLCM_SHDB,
oLCM_DCLK,
oLCM_HSYNC,
oLCM_VSYNC,
oLCM_SCLK,
LCM_SDAT,
oLCM_SCEN,
);
//===========================================================================
// PORT declarations
//===========================================================================
//////////////////////// Clock Input ////////////////////////
input iCLK_50; // 50 MHz
//////////////////////// Push Button ////////////////////////
input [3:0] iKEY; // Pushbutton[3:0]
//////////////////////////// LED ////////////////////////////
output [7:0] oLED; // LED [7:0]
//////////////////////////// 3.6' LCM Interface ////////////////////////////
output [7:0] oLCM_DATA; // LCM Data 8 Bits
output oLCM_GRST; // LCM Global Reset
output oLCM_SHDB; // LCM Sleep Mode
output oLCM_DCLK; // LCM Clcok
output oLCM_HSYNC; // LCM HSYNC
output oLCM_VSYNC; // LCM VSYNC
output oLCM_SCLK; // LCM I2C Clock
inout LCM_SDAT; // LCM I2C Data
output oLCM_SCEN; // LCM I2C Chip Enable
//=============================================================================
// REG/WIRE declarations
//=============================================================================
reg CLK_25; // clock 25 M hz
wire [7:0] LCM_DATA;
wire LCM_GRST;
wire LCM_SHDB;
wire LCM_DCLK;
wire LCM_HSYNC;
wire LCM_VSYNC;
wire LCM_SCLK;
wire LCM_SDAT;
wire LCM_SCEN;
wire DLY_RST_0;
//=============================================================================
// Structural coding
//=============================================================================
assign oLED = 8'hff;
// 50Mhz clock divide into 25 Mhz
always@(posedge iCLK_50)
begin
CLK_25 <= ~CLK_25;
end
// This fucntion is used for LCD color pattern generating
// and disply timing control
LCM_Display u1 (
.iCLK(CLK_25),
.iRST_N(iKEY[0]),
.iKEY1(iKEY[1]),
.oLCM_VSYNC(oLCM_VSYNC),
.oLCM_HSYNC(oLCM_HSYNC),
.oLCM_GRST(oLCM_GRST),
.oLCM_DCLK(oLCM_DCLK),
.oLCM_SHDB(oLCM_SHDB),
.oLCM_DATA(oLCM_DATA)
);
// This function is used for the register configuration of
// the LCD module
I2S_LCM_Config u2 ( // Host Side
.iCLK(iCLK_50),
.iRST_N(DLY_RST_0),
// I2C Side
.I2S_SCLK(oLCM_SCLK),
.I2S_SDAT(LCM_SDAT),
.I2S_SCEN(oLCM_SCEN)
);
Reset_Delay u3 (
.iCLK(iCLK_50),
.iRST(iKEY[0]),
.oRST_0(DLY_RST_0),
);
endmodule
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