lcm_display.v.bak

开发板原理图 需要做开发板的可以参考参考

module LCM_Display	(
					iCLK,
					iRST_N,
					iKEY1,
					oLCM_VSYNC,
                    oLCM_HSYNC,
					oLCM_GRST,
                    oLCM_DCLK,
                    oLCM_SHDB,
					oLCM_DATA
					);
//===========================================================================
// PARAMETER declarations
//===========================================================================

//	Horizontal Parameter	( Pixel )
parameter	H_SYNC_CYC	=	1;
parameter	H_SYNC_BACK	=	151;
parameter	H_SYNC_ACT	=	960;
parameter	H_SYNC_FRONT=	59;
parameter	H_SYNC_TOTAL=	1171;
//	Virtical Parameter		( Line )
parameter	V_SYNC_CYC	=	1;
parameter	V_SYNC_BACK	=	13;
parameter	V_SYNC_ACT	=	240;
parameter	V_SYNC_FRONT=	8;
parameter	V_SYNC_TOTAL=	262;

//===========================================================================
// PORT declarations
//===========================================================================					

input			iCLK;		// input clock (25M hz)
input			iRST_N;		// input reset
input			iKEY1;		// confituration key of the display mode  
output 			oLCM_VSYNC; // LCM VSYNC 
output      	oLCM_HSYNC; // LCM HSYNC
output			oLCM_GRST;	// LCM Reset
output      	oLCM_DCLK;	// LCM Clcok
output      	oLCM_SHDB;	// LCM Sleep Mode
output 	[7:0]	oLCM_DATA;	// LCM I2C Data

//=============================================================================
// REG/WIRE declarations
//=============================================================================

wire			LCM_GRST;            
wire            LCM_DCLK;            
wire            LCM_SHDB;            
                                     
wire			oLCM_VSYNC;          
wire            oLCM_HSYNC;          
wire	[7:0]	oLCM_DATA;          
                
reg		[10:0]	h_cnt;
reg		[10:0]	v_cnt;
reg		[7:0]	tmp_data;
reg				lcd_h_sync;
reg				lcd_v_sync;

wire	[1:0]	msel;
reg		[1:0]	mod_3;
reg 	[1:0] 	display_mode;
reg				key1_d2;
reg				key1_d1;


//=============================================================================
// Structural coding
//=============================================================================
assign	oLCM_GRST	=	iRST_N;
assign	oLCM_DCLK	=	~iCLK;
assign	oLCM_SHDB	=	1'b1;
assign	oLCM_VSYNC	=	lcd_v_sync;
assign	oLCM_HSYNC	=	lcd_h_sync;
assign	oLCM_DATA	=	(display_mode==2'b00)	?	tmp_data	:
						(display_mode==2'b01)	?	((mod_3==msel)	?	tmp_data	:	8'h00)	:
						(display_mode==2'b10)	?	8'h7F		:
													8'hFF;
assign	msel		=	(v_cnt<94)					?	2'b01	:
						(v_cnt>=94	&& v_cnt<174)	?	2'b10	:
	
														2'b00	;
//========================================================================
// This fuction is used for generating "cheange_display_mode" pulse
// when KEY[1] of the DEN board is in rising edge, cheange_display_mode 
// will high. 

always@(posedge iCLK or negedge iRST_N)
	begin
		if (!iRST_N)
			begin
				key1_d2 <= 0;
				key1_d1 <= 0;
			end
		else
			begin
				key1_d2 <= key1_d1;
				key1_d1 <= iKEY1;
			end
	end
			
assign cheange_display_mode = ({key1_d2,key1_d1}==2'b01) ? 1: 0;
//========================================================================

always@(posedge iCLK or negedge iRST_N)
	begin
		if (!iRST_N)
			display_mode <= 0;
		else if (cheange_display_mode)
			begin
				if (display_mode == 2'b11)
					display_mode <= 0;
				else	
					display_mode <= display_mode + 1;
			end		
	end 


always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		tmp_data	<=	8'h00;
		mod_3		<=	2'b00;	
	end
	else
	begin
		if(	h_cnt>H_SYNC_BACK && h_cnt<(H_SYNC_TOTAL-H_SYNC_FRONT) )
		begin
			if(mod_3<2'b10)
			mod_3	<=	mod_3+1'b1;
			else
			mod_3	<=	2'b00;
			tmp_data<=	tmp_data+1'b1;
		end
		else
		begin
			mod_3	<=	2'b00;
			tmp_data<=	8'h00;	
		end
	end
end

//	H_Sync Generator, Ref. 25 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		h_cnt		<=	0;
		lcd_h_sync	<=	0;
	end
	else
	begin
		//	H_Sync Counter
		if( h_cnt < H_SYNC_TOTAL )
		h_cnt	<=	h_cnt+1;
		else
		h_cnt	<=	0;
		//	H_Sync Generator
		if( h_cnt < H_SYNC_CYC )
		lcd_h_sync	<=	0;
		else
		lcd_h_sync	<=	1;
	end
end

//	V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		v_cnt		<=	0;
		lcd_v_sync	<=	0;
	end
	else
	begin
		//	When H_Sync Re-start
		if(h_cnt==0)
		begin
			//	V_Sync Counter
			if( v_cnt < V_SYNC_TOTAL )
			v_cnt	<=	v_cnt+1;
			else
			v_cnt	<=	0;
			//	V_Sync Generator
			if(	v_cnt < V_SYNC_CYC )
			lcd_v_sync	<=	0;
			else
			lcd_v_sync	<=	1;
		end
	end
end
						




endmodule