pwm_12bit.v

来自「开发板原理图 需要做开发板的可以参考参考」· Verilog 代码 · 共 40 行

module pwm_12bit(

	input CLOCK_50,

	input [11:0]value,

	output	reg PWM_o

);
// PWM MODEULE //

	reg [12:0]PWM_cnt;
	
	always @(posedge CLOCK_50) begin
	
	if (PWM_cnt[12]) 
	
		PWM_cnt=0;
	
	else
	
		PWM_cnt=PWM_cnt+1;
	end
	

// PWM duty //	
	
	always @(posedge CLOCK_50) begin
	
	if (PWM_cnt < (13'h1000 - value))
	
		PWM_o=0;
	
	else
	
		PWM_o=1;
	
	end
	
endmodule