den_lcm_test.tan.rpt

开发板原理图 需要做开发板的可以参考参考

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM2210F324C3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                 ; To                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+----------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 114.68 MHz ( period = 8.720 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[0]           ; I2S_LCM_Config:u5|mSetup_ST.0000             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.917 ns                ;
; N/A                                     ; 114.89 MHz ( period = 8.704 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[0]           ; I2S_LCM_Config:u5|mI2S_STR                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.909 ns                ;
; N/A                                     ; 123.15 MHz ( period = 8.120 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[1]           ; I2S_LCM_Config:u5|mSetup_ST.0000             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.617 ns                ;
; N/A                                     ; 123.40 MHz ( period = 8.104 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[1]           ; I2S_LCM_Config:u5|mI2S_STR                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.609 ns                ;
; N/A                                     ; 124.41 MHz ( period = 8.038 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Blue_1[7]                            ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.486 ns                ;
; N/A                                     ; 124.42 MHz ( period = 8.037 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Green_1[2]                           ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.485 ns                ;
; N/A                                     ; 124.44 MHz ( period = 8.036 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Green_1[7]                           ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.484 ns                ;
; N/A                                     ; 124.46 MHz ( period = 8.035 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Green_1[4]                           ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.483 ns                ;
; N/A                                     ; 124.56 MHz ( period = 8.028 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Green_1[3]                           ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.476 ns                ;
; N/A                                     ; 124.60 MHz ( period = 8.026 ns )                    ; TCON:u4|HsynCnt[5]                                   ; TCON:u4|Blue_1[2]                            ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.474 ns                ;
; N/A                                     ; 125.88 MHz ( period = 7.944 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[3]           ; I2S_LCM_Config:u5|mSetup_ST.0000             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.529 ns                ;
; N/A                                     ; 126.14 MHz ( period = 7.928 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[3]           ; I2S_LCM_Config:u5|mI2S_STR                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.521 ns                ;
; N/A                                     ; 127.39 MHz ( period = 7.850 ns )                    ; I2S_LCM_Config:u5|mI2S_DATA[2]                       ; I2S_LCM_Config:u5|I2S_Controller:u0|mSDATA   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.482 ns                ;
; N/A                                     ; 128.01 MHz ( period = 7.812 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK_DIV[3]  ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.741 ns                ;
; N/A                                     ; 129.27 MHz ( period = 7.736 ns )                    ; I2S_LCM_Config:u5|mI2S_DATA[1]                       ; I2S_LCM_Config:u5|I2S_Controller:u0|mSDATA   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.425 ns                ;
; N/A                                     ; 129.85 MHz ( period = 7.701 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK_DIV[10] ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.966 ns                ;
; N/A                                     ; 129.89 MHz ( period = 7.699 ns )                    ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK_DIV[5]  ; I2S_LCM_Config:u5|I2S_Controller:u0|mI2S_CLK ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.628 ns                ;
; N/A                                     ; 130.79 MHz ( period = 7.646 ns )                    ; I2S_LCM_Config:u5|mI2S_DATA[0]                       ; I2S_LCM_Config:u5|I2S_Controller:u0|mSDATA   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.380 ns                ;