den_lcm_test.tan.rpt
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RPT
276 行
Classic Timing Analyzer report for DEN_LCM_Test
Tue May 01 13:28:13 2007
Quartus II Version 7.1 Build 154 04/18/2007 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLOCK_50'
6. Clock Hold: 'CLOCK_50'
7. tsu
8. tco
9. th
10. Timing Analyzer INI Usage
11. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------+----------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------+----------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 1.200 ns ; GPIO_0[0] ; touch_init:u1|Touch_en ; -- ; CLOCK_50 ; 0 ;
; Worst-case tco ; N/A ; None ; 13.158 ns ; touch_init:u1|Display_mode[0] ; GPIO_0[31] ; CLOCK_50 ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.854 ns ; GPIO_0[0] ; touch_init:u1|Touch_en ; -- ; CLOCK_50 ; 0 ;
; Clock Setup: 'CLOCK_50' ; N/A ; None ; 114.68 MHz ( period = 8.720 ns ) ; I2S_LCM_Config:u5|I2S_Controller:u0|mST[0] ; I2S_LCM_Config:u5|mSetup_ST.0000 ; CLOCK_50 ; CLOCK_50 ; 0 ;
; Clock Hold: 'CLOCK_50' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; Reset_Delay:u6|oRST_1 ; I2S_LCM_Config:u5|mI2S_DATA[13] ; CLOCK_50 ; CLOCK_50 ; 2 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 2 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------+----------------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
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