prev_cmp_denano.qmsg

开发板原理图 需要做开发板的可以参考参考

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 154 04/18/2007 SJ Web Edition " "Info: Version 7.1 Build 154 04/18/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 02 00:00:05 2007 " "Info: Processing started: Wed May 02 00:00:05 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DEnano -c DEnano " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DEnano -c DEnano" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Allocated 128 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 02 00:00:09 2007 " "Info: Processing ended: Wed May 02 00:00:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 154 04/18/2007 SJ Web Edition " "Info: Version 7.1 Build 154 04/18/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 02 00:00:10 2007 " "Info: Processing started: Wed May 02 00:00:10 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DEnano -c DEnano " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DEnano -c DEnano" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 3 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register Traffic_Light:m\|Cont\[21\] register Traffic_Light:m\|mLED\[1\] 118.91 MHz 8.41 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 118.91 MHz between source register \"Traffic_Light:m\|Cont\[21\]\" and destination register \"Traffic_Light:m\|mLED\[1\]\" (period= 8.41 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.967 ns + Longest register register " "Info: + Longest register to register delay is 7.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Traffic_Light:m\|Cont\[21\] 1 REG LC_X16_Y8_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y8_N2; Fanout = 9; REG Node = 'Traffic_Light:m\|Cont\[21\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Traffic_Light:m|Cont[21] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(0.319 ns) 2.199 ns Traffic_Light:m\|always0~2332 2 COMB LC_X16_Y7_N4 3 " "Info: 2: + IC(1.880 ns) + CELL(0.319 ns) = 2.199 ns; Loc. = LC_X16_Y7_N4; Fanout = 3; COMB Node = 'Traffic_Light:m\|always0~2332'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.199 ns" { Traffic_Light:m|Cont[21] Traffic_Light:m|always0~2332 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.319 ns) 3.006 ns Traffic_Light:m\|mode\[0\]~216 3 COMB LC_X16_Y7_N5 3 " "Info: 3: + IC(0.488 ns) + CELL(0.319 ns) = 3.006 ns; Loc. = LC_X16_Y7_N5; Fanout = 3; COMB Node = 'Traffic_Light:m\|mode\[0\]~216'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.807 ns" { Traffic_Light:m|always0~2332 Traffic_Light:m|mode[0]~216 } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.647 ns) + CELL(0.319 ns) 4.972 ns Traffic_Light:m\|mLED~492 4 COMB LC_X15_Y6_N1 1 " "Info: 4: + IC(1.647 ns) + CELL(0.319 ns) = 4.972 ns; Loc. = LC_X15_Y6_N1; Fanout = 1; COMB Node = 'Traffic_Light:m\|mLED~492'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { Traffic_Light:m|mode[0]~216 Traffic_Light:m|mLED~492 } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.571 ns) 6.262 ns Traffic_Light:m\|mLED~497 5 COMB LC_X14_Y6_N9 1 " "Info: 5: + IC(0.719 ns) + CELL(0.571 ns) = 6.262 ns; Loc. = LC_X14_Y6_N9; Fanout = 1; COMB Node = 'Traffic_Light:m\|mLED~497'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { Traffic_Light:m|mLED~492 Traffic_Light:m|mLED~497 } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.125 ns) 6.832 ns Traffic_Light:m\|mLED~498 6 COMB LC_X14_Y6_N0 2 " "Info: 6: + IC(0.445 ns) + CELL(0.125 ns) = 6.832 ns; Loc. = LC_X14_Y6_N0; Fanout = 2; COMB Node = 'Traffic_Light:m\|mLED~498'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { Traffic_Light:m|mLED~497 Traffic_Light:m|mLED~498 } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.663 ns) 7.967 ns Traffic_Light:m\|mLED\[1\] 7 REG LC_X14_Y6_N5 1 " "Info: 7: + IC(0.472 ns) + CELL(0.663 ns) = 7.967 ns; Loc. = LC_X14_Y6_N5; Fanout = 1; REG Node = 'Traffic_Light:m\|mLED\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.135 ns" { Traffic_Light:m|mLED~498 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.316 ns ( 29.07 % ) " "Info: Total cell delay = 2.316 ns ( 29.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.651 ns ( 70.93 % ) " "Info: Total interconnect delay = 5.651 ns ( 70.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { Traffic_Light:m|Cont[21] Traffic_Light:m|always0~2332 Traffic_Light:m|mode[0]~216 Traffic_Light:m|mLED~492 Traffic_Light:m|mLED~497 Traffic_Light:m|mLED~498 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { Traffic_Light:m|Cont[21] Traffic_Light:m|always0~2332 Traffic_Light:m|mode[0]~216 Traffic_Light:m|mLED~492 Traffic_Light:m|mLED~497 Traffic_Light:m|mLED~498 Traffic_Light:m|mLED[1] } { 0.000ns 1.880ns 0.488ns 1.647ns 0.719ns 0.445ns 0.472ns } { 0.000ns 0.319ns 0.319ns 0.319ns 0.571ns 0.125ns 0.663ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.472 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLOCK_50 1 CLK PIN_J6 36 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J6; Fanout = 36; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.574 ns) 2.472 ns Traffic_Light:m\|mLED\[1\] 2 REG LC_X14_Y6_N5 1 " "Info: 2: + IC(1.171 ns) + CELL(0.574 ns) = 2.472 ns; Loc. = LC_X14_Y6_N5; Fanout = 1; REG Node = 'Traffic_Light:m\|mLED\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { CLOCK_50 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 52.63 % ) " "Info: Total cell delay = 1.301 ns ( 52.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.171 ns ( 47.37 % ) " "Info: Total interconnect delay = 1.171 ns ( 47.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|mLED[1] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.472 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLOCK_50 1 CLK PIN_J6 36 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J6; Fanout = 36; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.574 ns) 2.472 ns Traffic_Light:m\|Cont\[21\] 2 REG LC_X16_Y8_N2 9 " "Info: 2: + IC(1.171 ns) + CELL(0.574 ns) = 2.472 ns; Loc. = LC_X16_Y8_N2; Fanout = 9; REG Node = 'Traffic_Light:m\|Cont\[21\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { CLOCK_50 Traffic_Light:m|Cont[21] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 52.63 % ) " "Info: Total cell delay = 1.301 ns ( 52.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.171 ns ( 47.37 % ) " "Info: Total interconnect delay = 1.171 ns ( 47.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|Cont[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|Cont[21] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|mLED[1] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|Cont[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|Cont[21] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { Traffic_Light:m|Cont[21] Traffic_Light:m|always0~2332 Traffic_Light:m|mode[0]~216 Traffic_Light:m|mLED~492 Traffic_Light:m|mLED~497 Traffic_Light:m|mLED~498 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { Traffic_Light:m|Cont[21] Traffic_Light:m|always0~2332 Traffic_Light:m|mode[0]~216 Traffic_Light:m|mLED~492 Traffic_Light:m|mLED~497 Traffic_Light:m|mLED~498 Traffic_Light:m|mLED[1] } { 0.000ns 1.880ns 0.488ns 1.647ns 0.719ns 0.445ns 0.472ns } { 0.000ns 0.319ns 0.319ns 0.319ns 0.571ns 0.125ns 0.663ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|mLED[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|mLED[1] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|Cont[21] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|Cont[21] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LED\[6\] Traffic_Light:m\|mLED\[6\] 6.591 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LED\[6\]\" through register \"Traffic_Light:m\|mLED\[6\]\" is 6.591 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.472 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLOCK_50 1 CLK PIN_J6 36 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J6; Fanout = 36; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.574 ns) 2.472 ns Traffic_Light:m\|mLED\[6\] 2 REG LC_X13_Y7_N4 1 " "Info: 2: + IC(1.171 ns) + CELL(0.574 ns) = 2.472 ns; Loc. = LC_X13_Y7_N4; Fanout = 1; REG Node = 'Traffic_Light:m\|mLED\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { CLOCK_50 Traffic_Light:m|mLED[6] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 52.63 % ) " "Info: Total cell delay = 1.301 ns ( 52.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.171 ns ( 47.37 % ) " "Info: Total interconnect delay = 1.171 ns ( 47.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|mLED[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|mLED[6] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.884 ns + Longest register pin " "Info: + Longest register to pin delay is 3.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Traffic_Light:m\|mLED\[6\] 1 REG LC_X13_Y7_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y7_N4; Fanout = 1; REG Node = 'Traffic_Light:m\|mLED\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Traffic_Light:m|mLED[6] } "NODE_NAME" } } { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.430 ns) + CELL(1.454 ns) 3.884 ns LED\[6\] 2 PIN PIN_V4 0 " "Info: 2: + IC(2.430 ns) + CELL(1.454 ns) = 3.884 ns; Loc. = PIN_V4; Fanout = 0; PIN Node = 'LED\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.884 ns" { Traffic_Light:m|mLED[6] LED[6] } "NODE_NAME" } } { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 37.44 % ) " "Info: Total cell delay = 1.454 ns ( 37.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.430 ns ( 62.56 % ) " "Info: Total interconnect delay = 2.430 ns ( 62.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.884 ns" { Traffic_Light:m|mLED[6] LED[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.884 ns" { Traffic_Light:m|mLED[6] LED[6] } { 0.000ns 2.430ns } { 0.000ns 1.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.472 ns" { CLOCK_50 Traffic_Light:m|mLED[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.472 ns" { CLOCK_50 CLOCK_50~combout Traffic_Light:m|mLED[6] } { 0.000ns 0.000ns 1.171ns } { 0.000ns 0.727ns 0.574ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.884 ns" { Traffic_Light:m|mLED[6] LED[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.884 ns" { Traffic_Light:m|mLED[6] LED[6] } { 0.000ns 2.430ns } { 0.000ns 1.454ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 02 00:00:12 2007 " "Info: Processing ended: Wed May 02 00:00:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Info: Quartus II Full Compilation was successful. 0 errors, 19 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}