prev_cmp_denano.qmsg

开发板原理图 需要做开发板的可以参考参考

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 154 04/18/2007 SJ Web Edition " "Info: Version 7.1 Build 154 04/18/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 01 23:59:59 2007 " "Info: Processing started: Tue May 01 23:59:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DEnano -c DEnano " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DEnano -c DEnano" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "DEnano.v(18) " "Warning (10275): Verilog HDL Module Instantiation warning at DEnano.v(18): ignored dangling comma in List of Port Connections" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 18 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DEnano.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DEnano.v" { { "Info" "ISGN_ENTITY_NAME" "1 DEnano " "Info: Found entity 1: DEnano" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Traffic_Light.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Traffic_Light.v" { { "Info" "ISGN_ENTITY_NAME" "1 Traffic_Light " "Info: Found entity 1: Traffic_Light" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DEnano " "Info: Elaborating entity \"DEnano\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Traffic_Light Traffic_Light:m " "Info: Elaborating entity \"Traffic_Light\" for hierarchy \"Traffic_Light:m\"" {  } { { "DEnano.v" "m" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 18 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "timer Traffic_Light.v(8) " "Warning (10036): Verilog HDL or VHDL warning at Traffic_Light.v(8): object \"timer\" assigned a value but never read" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 8 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 Traffic_Light.v(38) " "Warning (10230): Verilog HDL assignment warning at Traffic_Light.v(38): truncated value with size 32 to match size of target (3)" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 Traffic_Light.v(44) " "Warning (10230): Verilog HDL assignment warning at Traffic_Light.v(44): truncated value with size 32 to match size of target (3)" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 Traffic_Light.v(62) " "Warning (10230): Verilog HDL assignment warning at Traffic_Light.v(62): truncated value with size 32 to match size of target (3)" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Traffic_Light:m\|mLED\[4\] data_in GND " "Warning: Reduced register \"Traffic_Light:m\|mLED\[4\]\" with stuck data_in port to stuck value GND" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Traffic_Light:m\|mLED\[0\] data_in GND " "Warning: Reduced register \"Traffic_Light:m\|mLED\[0\]\" with stuck data_in port to stuck value GND" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Traffic_Light:m\|mode\[2\] data_in GND " "Warning: Reduced register \"Traffic_Light:m\|mode\[2\]\" with stuck data_in port to stuck value GND" {  } { { "Traffic_Light.v" "" { Text "D:/DEN/Traffic Light Mode/Traffic_Light.v" 77 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[0\] VCC " "Warning: Pin \"LED\[0\]\" stuck at VCC" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[4\] VCC " "Warning: Pin \"LED\[4\]\" stuck at VCC" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning: No output dependent on input pin \"KEY\[1\]\"" {  } { { "DEnano.v" "" { Text "D:/DEN/Traffic Light Mode/DEnano.v" 4 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "109 " "Info: Implemented 109 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 02 00:00:01 2007 " "Info: Processing ended: Wed May 02 00:00:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}