denano.tan.rpt

开发板原理图 需要做开发板的可以参考参考

; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[23] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.737 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[20] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.737 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[19] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.737 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[27] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.728 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[24] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.728 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[26] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.728 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[6]  ; Traffic_Light:m|Cont[25] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.728 ns                ;
; N/A                                     ; Restricted to 304.04 MHz ( period = 3.289 ns )      ; Traffic_Light:m|Cont[0]  ; Traffic_Light:m|Cont[2]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.724 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                          ;                          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+-------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                    ; To     ; From Clock ;
+-------+--------------+------------+-------------------------+--------+------------+
; N/A   ; None         ; 6.313 ns   ; Traffic_Light:m|mLED[6] ; LED[6] ; CLOCK_50   ;
; N/A   ; None         ; 6.290 ns   ; Traffic_Light:m|mLED[3] ; LED[3] ; CLOCK_50   ;
; N/A   ; None         ; 6.240 ns   ; Traffic_Light:m|mLED[7] ; LED[7] ; CLOCK_50   ;
; N/A   ; None         ; 6.197 ns   ; Traffic_Light:m|mLED[5] ; LED[5] ; CLOCK_50   ;
; N/A   ; None         ; 6.191 ns   ; Traffic_Light:m|mLED[1] ; LED[1] ; CLOCK_50   ;
; N/A   ; None         ; 5.554 ns   ; Traffic_Light:m|mLED[2] ; LED[2] ; CLOCK_50   ;
+-------+--------------+------------+-------------------------+--------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer INI Usage                                                                                                                 ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+
; Option               ; Usage                                                                                                              ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+
; Initialization file: ; c:/altera/71/quartus/bin/quartus.ini                                                                               ;
; dev_password         ; e81f0e65b8afc1da24522b894c886f598ff5e3fafae3453dd1029e508011004342234235215526025211557545361520042000410042555455 ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 154 04/18/2007 SJ Web Edition
    Info: Processing started: Wed May 02 00:01:41 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DEnano -c DEnano
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK_50" is an undefined clock
Info: Clock "CLOCK_50" has Internal fmax of 121.68 MHz between source register "Traffic_Light:m|Cont[5]" and destination register "Traffic_Light:m|mLED[1]" (period= 8.218 ns)
    Info: + Longest register to register delay is 7.775 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y8_N6; Fanout = 5; REG Node = 'Traffic_Light:m|Cont[5]'
        Info: 2: + IC(1.351 ns) + CELL(0.571 ns) = 1.922 ns; Loc. = LC_X13_Y9_N4; Fanout = 1; COMB Node = 'Traffic_Light:m|Equal1~236'
        Info: 3: + IC(0.472 ns) + CELL(0.319 ns) = 2.713 ns; Loc. = LC_X13_Y9_N3; Fanout = 3; COMB Node = 'Traffic_Light:m|Equal1~237'
        Info: 4: + IC(1.686 ns) + CELL(0.125 ns) = 4.524 ns; Loc. = LC_X13_Y8_N0; Fanout = 1; COMB Node = 'Traffic_Light:m|LessThan4~418'
        Info: 5: + IC(0.191 ns) + CELL(0.125 ns) = 4.840 ns; Loc. = LC_X13_Y8_N1; Fanout = 1; COMB Node = 'Traffic_Light:m|always0~2319'
        Info: 6: + IC(1.232 ns) + CELL(0.571 ns) = 6.643 ns; Loc. = LC_X12_Y7_N1; Fanout = 2; COMB Node = 'Traffic_Light:m|mLED~492'
        Info: 7: + IC(0.469 ns) + CELL(0.663 ns) = 7.775 ns; Loc. = LC_X12_Y7_N6; Fanout = 1; REG Node = 'Traffic_Light:m|mLED[1]'
        Info: Total cell delay = 2.374 ns ( 30.53 % )
        Info: Total interconnect delay = 5.401 ns ( 69.47 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLOCK_50" to destination register is 2.472 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J6; Fanout = 36; CLK Node = 'CLOCK_50'
            Info: 2: + IC(1.171 ns) + CELL(0.574 ns) = 2.472 ns; Loc. = LC_X12_Y7_N6; Fanout = 1; REG Node = 'Traffic_Light:m|mLED[1]'
            Info: Total cell delay = 1.301 ns ( 52.63 % )
            Info: Total interconnect delay = 1.171 ns ( 47.37 % )
        Info: - Longest clock path from clock "CLOCK_50" to source register is 2.472 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_J6; Fanout = 36; CLK Node = 'C