knight_rider.v

来自「开发板原理图 需要做开发板的可以参考参考」· Verilog 代码 · 共 34 行

module Knight_Rider(LED,CLOCK_50,KEY);
output	[7:0]	LED;
input			CLOCK_50;
input			KEY;

reg		[22:0]	Cont;
reg		[7:0]	mLED;
reg				DIR;

always@(posedge CLOCK_50)	Cont	<=	Cont+1'b1;

always@(posedge Cont[22] or negedge KEY)
begin
	if(!KEY)
	begin
		mLED	<=	8'b11100000;
		DIR		<=	1;
	end
	else
	begin
		if(!DIR)
		mLED	<=	{mLED[6:0],1'b0};
		else
		mLED	<=	{1'b0,mLED[7:1]};
		if(mLED == 8'b01110000)
		DIR	<=	1;
		else if(mLED == 8'b00001110)
		DIR	<=	0;
	end
end

assign	LED	=	~mLED;

endmodule