k9f5608.c

这是英贝特试验箱jiffs测试代码 喊难找的啊

/*
 *  drivers/mtd/nand/s3c44b0.c
 *
 *  Copyright (C) 2000 Steven J. Hill ([e-mail])
 *
 *
 *	10-29-2001 TG	change to support hardwarespecific access
 *			to controllines	(due to change in nand.c)
 *			page_cache added
 *
 * $Id: s3c44b0.c,v 1.16 2002/03/05 13:50:47 dwmw2 Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   s3c44b0 board which utilizes the Toshiba TC58V64AFT part. This is
 *   a 64Mibit (8MiB x 8 bits) NAND flash device.
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include "k9f5608.h"

/*
 * MTD structure for s3c44b0 board
 */
static struct mtd_info *s3c44b0_mtd = NULL;

/*
* IO offset to Port data register
* where the CLE, ALE and NCE pins
* are wired to.
*/
#define S3C44B0_PEDR		0x0038	
	
/*
* IO offset to Port control register
* so we can control the IO lines.
*/
#define S3C44B0_PEDDR		0x0034		


/*
 * Module stuff
 */

static int s3c44b0_io_base = S3C44B0_IO_BASE;
static int s3c44b0_fio_base = S3C44B0_FIO_BASE;
static int s3c44b0_pedr = S3C44B0_PEDR;
static int s3c44b0_peddr = S3C44B0_PEDDR;

#ifdef MODULE
MODULE_PARM(s3c44b0_io_base, "i");
MODULE_PARM(s3c44b0_fio_base, "i");
MODULE_PARM(s3c44b0_pedr, "i");
MODULE_PARM(s3c44b0_peddr, "i");

__setup("s3c44b0_io_base = ", s3c44b0_io_base);
__setup("s3c44b0_fio_base = ", s3c44b0_fio_base);
__setup("s3c44b0_pedr = ", s3c44b0_pedr);
__setup("s3c44b0_peddr = ", s3c44b0_peddr);
#endif

/*
 * Define partitions for flash device
 */
const static struct mtd_partition partition_info[] = {
	{ name: "S3CEduKit-II jffs2 partition",
	  offset: 0,
	  size: 16*1024*1024 },
	{ name: "jffs2 partition",
	  offset: MTDPART_OFS_APPEND,
	  size: 16*1024*1024 },
};
#define NUM_PARTITIONS 2


/* 
 *	hardware specific access to control-lines
*/
void s3c44b0_hwcontrol(int cmd) {
    switch(cmd){
	case NAND_CTL_SETCLE: (*(volatile unsigned *)(s3c44b0_io_base + PD_CLE)) |=  CLE; break;
	case NAND_CTL_CLRCLE: (*(volatile unsigned *)(s3c44b0_io_base + PD_CLE)) &= ~CLE; break;

	case NAND_CTL_SETALE: (*(volatile unsigned *)(s3c44b0_io_base + PD_ALE)) |=  ALE; break;
	case NAND_CTL_CLRALE: (*(volatile unsigned *)(s3c44b0_io_base + PD_ALE)) &= ~ALE; break;

	case NAND_CTL_SETNCE: (*(volatile unsigned *)(s3c44b0_io_base + PD_CE)) |= CE; break;
	case NAND_CTL_CLRNCE: (*(volatile unsigned *)(s3c44b0_io_base + PD_CE)) &= ~CE; break;

    }
}

/*
 * Main initialization routine
 */
int __init s3c44b0_init (void)
{
	int i;
	struct nand_chip *this;

	/* Allocate memory for MTD device structure and private data */
	s3c44b0_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
				GFP_KERNEL);
	if (!s3c44b0_mtd) {
		printk ("Unable to allocate s3c44b0 NAND MTD device structure.\n");
		return -ENOMEM;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *) (&s3c44b0_mtd[1]);

	/* Initialize structures */
	memset((char *) s3c44b0_mtd, 0, sizeof(struct mtd_info));
	memset((char *) this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	s3c44b0_mtd->priv = this;

	/*
	 * Set GPIO Port F control register so that the pins are configured
	 * to be outputs for controlling the NAND flash.
	 */
	// Embest EduKit44b0
	(*(volatile unsigned *)(s3c44b0_io_base + PA_ALE)) |= ((1<<18)|(1<<16));//0x0FF5FF55;   // GPC8:ALE - output([17:16]=01); GPC9:CLE - output([19:18]=01)
	(*(volatile unsigned *)(s3c44b0_io_base + PA_ALE)) &= ~((1<<19)|(1<<17));
	(*(volatile unsigned *)(s3c44b0_io_base + PA_CE)) &= ~(1<<9);      // GPB9:nFCE - output([9]=0)
	(*(volatile unsigned *)(s3c44b0_io_base + PA_RB)) &= ~(1<<5|1<<4); // GPF2:R/B - input([5:4]=00)
	//(*(volatile unsigned *)(s3c44b0_io_base + s3c44b0_peddr)) = 0x002500; // S3CEV40
	//(*(volatile unsigned char*) (s3c44b0_io_base + s3c44b0_pedr)) = 0xff;
	//for (i=0;i<3000;i++);
	
	/* Set address of NAND IO lines */
	this->IO_ADDR_R = s3c44b0_fio_base;
	this->IO_ADDR_W = s3c44b0_fio_base;
	/* Set address of hardware control function */
	this->hwcontrol = s3c44b0_hwcontrol;
	/* 15 us command delay time */
	this->chip_delay = 15;		

	/* Scan to find existence of the device */
	if (nand_scan (s3c44b0_mtd)) {
		kfree (s3c44b0_mtd);
		return -ENXIO;
	}

	/* Allocate memory for internal data buffer */
	this->data_buf = kmalloc (sizeof(u_char) * (s3c44b0_mtd->oobblock + s3c44b0_mtd->oobsize), GFP_KERNEL);
	if (!this->data_buf) {
		printk ("Unable to allocate NAND data buffer for s3c44b0.\n");
		kfree (s3c44b0_mtd);
		return -ENOMEM;
	}

	/* Allocate memory for internal data buffer */
	this->data_cache = kmalloc (sizeof(u_char) * (s3c44b0_mtd->oobblock + s3c44b0_mtd->oobsize), GFP_KERNEL);
	if (!this->data_cache) {
		printk ("Unable to allocate NAND data cache for s3c44b0.\n");
		kfree (this->data_buf);
		kfree (s3c44b0_mtd);
		return -ENOMEM;
	}
	this->cache_page = -1;

	/* Register the partitions */
		add_mtd_partitions(s3c44b0_mtd, (struct mtd_partition *)partition_info, NUM_PARTITIONS);

	/* Return happy */
	return 0;
}
module_init(s3c44b0_init);

/*
 * Clean up routine
 */
#ifdef MODULE
static void __exit s3c44b0_cleanup (void)
{
	struct nand_chip *this = (struct nand_chip *) &s3c44b0_mtd[1];

	/* Unregister the device */
	del_mtd_device (s3c44b0_mtd);

	/* Free internal data buffer */
	kfree (this->data_buf);
	kfree (this->page_cache);

	/* Free the MTD device structure */
	kfree (s3c44b0_mtd);
}
module_exit(s3c44b0_cleanup);
#endif

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Steven J. Hill <[e-mail]");
MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on s3c44b0 board");