pfc_ctrl.h

boost-pfc升压型功率因素校正程序

#ifndef __PFC_CTRL_H
#define __PFC_CTRL_H

//_____ D E F I N I T I O N S ______________________________________________

//#define PWM_PFC_C 
#define PSC_PFC_C 

#define PFC_PIN  0       //PORTD.0
#define PFC_PORT PORTD   //PORTD.0
#define PFC_DDR  DDRD    //PORTD.0
#define PFC_IND   PIND   //PORTD.0

//外部晶振8M系统
#define  PWM_FRE       8000000 //8M
#define  PFC_FRE       8000    //8M
#define  Ki   7500             //180v

#define PFC_OFF                                    0
#define INIT_PFC_CHECK                             1
#define VIN_CHECK                                  2 //!< Check the value of the main haversine
#define CONFIGURE_PFC_SOFT_START                   3 //!< The PFC is Off until the haversine and v_bus are within specification
#define START_PFC_SOFT_START                       4 //!< haversine is within specification the psc0 has to be initialized before starting the PFC soft start
#define PFC_WAIT                                   5
#define OUT_OVER_V                                 6
#define PFC_SOFT_CONTROL                           7
#define PFC_PROBLEM                                8
#define SHUT_DOWN_PFC_AND_SLOW_DOWN_UC_SPEED       9 //!< Control, PFC and lamp tasks are active


//PSC ---------------------------控制参数
#define VIN_MAX                    (300*14/10) //最大输入电压 260V *1.414 = 峰值电压
#define VIN_MIN                    (100*14/10) //最小输入电压 170V
#define HAVERSINE_PEAK_MAX         ((VIN_MAX*1023L*22)/((2000+22)*5))  //22-2000 = 3.38 =690
#define HAVERSINE_PEAK_MIN         ((VIN_MIN*1023L*22)/((2000+22)*5))  //22-2000 = 1.84 =378

//PFC脉宽控制定义值
#define PFC_START_PULSE                   10 //!< TEN_US with CKDIV8
#define PFC_START_PERIOD                  40 //!< FIFTY_US with CKDIV8
#define PFC_MAX_PERIOD                  2560 //!< (40*64) // FORTY_US
#define PFC_MAX_PULSE                   900 //!< (25*64) // TWENTY_FIVE_US（40k） Highest pulse applicable


#define PFC_MAX_START_SHOTS                   16 //!< number of PFC start cycles
#define PFC_START_MAX_TRIES                   20 //!< number of soft start tries before considering there is a problem

#define V_BUS_OVERSHOOT                      PFC_V_440V  //440v
#define V_BUS_SET_POINT                      PFC_V_OUT   //400v

#define Enable_comparator0()                          (AC0CON |= (1<<AC0EN) ) //AC0EN模拟比较器0使能位，AC0CON模拟比较器0控制寄存器，将AC0M1的值替换为AC0EN

#define Enable_comparator0_interrupt()                (AC0CON |=  (1<<AC0IE) )//AC0IE模拟比较器0中断使能位，
#define Disable_comparator0_interrupt()               (AC0CON &= ~(1<<AC0IE) ) 
#define Comparator0_it_on_output_toggle()                                     \
    (AC0CON &= ~(  (1<<AC0IS1) | (1<<AC0IS0) ) ) 
//! Comparator 0 interrupt on_output falling edge
#define Comparator0_it_on_output_falling_edge()                               \
    (AC0CON |=  (1<<AC0IS1),                                           \
    AC0CON &= ~(1<<AC0IS0) )
//! Comparator 0 interrupt on_output rising edge
#define Comparator0_it_on_output_rising_edge()                                \
    (AC0CON |=  ((1<<AC0IS1) | (1<<AC0IS0)) ) 

//! Set the negative input comparator 0 as Vref/6.40V
#define Set_comparator0_ni_vref_6_40()                                        \
    (AC0CON &= ~( (1<<AC0M2) | (1<<AC0M1) | (1<<AC0M0) ) ) 
//! Set Vref/3.20V as the negative input comparator 0
#define Set_comparator0_ni_vref_3_20()                                        \
    (AC0CON &= ~( (1<<AC0M2) | (1<<AC0M1) |  (0<<AC0M0) ),             \
    AC0CON |=  ( (0<<AC0M2) | (0<<AC0M1) |  (1<<AC0M0) ) ) 
//! Set Vref/2.13V as the negative input comparator 0
#define Set_comparator0_ni_vref_2_13()                                        \
    (AC0CON &= ~( (1<<AC0M2) | (0<<AC0M1) |  (1<<AC0M0) ),             \
    AC0CON |=  ( (0<<AC0M2) | (1<<AC0M1) |  (0<<AC0M0) ) ) 
//! Set Vref/1.60V as the negative input comparator 0
#define Set_comparator0_ni_vref_1_60()                                        \
    (AC0CON &= ~( (1<<AC0M2) | (0<<AC0M1) |  (0<<AC0M0) ),             \
    AC0CON |=  ( (0<<AC0M2) | (1<<AC0M1) |  (1<<AC0M0) ) ) 
//! Set the ACMPM pin as the negative input comparator 0
#define Set_comparator0_ni_acmp()                                             \
    (AC0CON &= ~( (0<<AC0M2) | (1<<AC0M1) |  (1<<AC0M0) ),             \
    AC0CON |=  ( (1<<AC0M2) | (0<<AC0M1) |  (0<<AC0M0) ) ) 
//! Set the DAC output as the negative input comparator 0
#define Set_comparator0_ni_dac()                                              \
    (AC0CON &= ~( (0<<AC0M2) | (1<<AC0M1) |  (0<<AC0M0) ),             \
    AC0CON |=  ( (1<<AC0M2) | (0<<AC0M1) |  (1<<AC0M0) ) ) 
//! @}
#define Disable_comparator0()                         (AC0CON &= ~(1<<AC0EN) )  


#define Enable_pscout00()                             (PSOC0 |=  (1<<POEN0A) )  //!< Enable PSC0 Waveform Generator A
#define Disable_pscout00()                            (PSOC0 &= ~(1<<POEN0A) )  //!< Disable PSC0 Waveform Generator A

#define Enable_pscout01()                             (PSOC0 |=  (1<<POEN0B) )  //!< Enable PSC0 错Waveform Generator B
#define Disable_pscout01()                            (PSOC0 &= ~(1<<POEN0B) )  //!< Disable PSC0 Waveform Generator B
//! Enable Both PSC0 Waveform Generator A and B
#define Enable_both_psc0_outputs()                                            \
    (PSOC0 |=  ((1<<POEN0A) | (1<<POEN0B)))
//! Disable Both PSC0 Waveform Generator A and B
#define Disable_both_psc0_outputs()                                           \
    (PSOC0 &= ~((1<<POEN0A) | (1<<POEN0B)))

#define Psc0_outputs_active_high()                    (PCNF0 |=  (1<<POP0) )    //PCNF0是PSC0的配置寄存器!< PSC0 outputs are active high
#define Psc0_outputs_active_low()                     (PCNF0 &= ~(1<<POP0) )    //!< PSC0 outputs are active low
#define Enable_psc0_fifty_percent_mode()              (PCNF0 |=  (1<<PFIFTY0) )  //!< PSC0 is in 50% mode: Only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0R/SAH/L during the update of OCR0BH/L
#define Disable_psc0_fifty_percent_mode()             (PCNF0 &= ~(1<<PFIFTY0) )  //!< OCR0R/SAH/L and OCR0R/SBH/L are fully independant

#define Enable_psc0_autolock_mode()                   (PCNF0 |=  (1<<PALOCK0) )  //!< OCR0R/SAH/L and OCR0R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR0RB has been last written
#define Disable_psc0_autolock_mode()                  (PCNF0 &= ~(1<<PALOCK0) )  //!< The update will be procced according to PLOCK0 bit

#define Lock_psc0_compare_values()                    (PCNF0 |=  (1<<PLOCK0) )   //!< Take care that the lock is active only if you have disabled the autolock mode
#define Update_psc0_compare_values()                  (PCNF0 &= ~(1<<PLOCK0) )   //!< The compare registers will be updated with the content of OCR0ARH/L and OCR0BRH

#define Psc0_use_pll_clock()                          (PCNF0 |= (1<<PCLKSEL0) )  //! Connect the PSC0 input clock to the PLL

#define Psc0_use_io_clock()                           (PCNF0 &= ~(1<<PCLKSEL0) ) //! Connect the PSC0 input clock to the I/O clock

//! Start the PLL at 64MHz and connect it to PSC0
#define Psc0_use_64_mega_pll_clock()                                          \  
    (Start_pll_64_mega(),                                               \
    Wait_pll_ready(),                                                  \
    Psc0_use_pll_clock() )
//! Start the PLL at 32MHz and connect it to PSC0
#define Psc0_use_32_mega_pll_clock()                                          \