📄 disp_br2.h
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///////////////////////////////////////////////////////////////////
// Definitions for Display Port
#define SINGLE_PORT 0x00 // Single port (Single pixel output)
#define DOUBLE_PORT 0x04 // Double port (Double pixel output)
#define DISPLAY_PORT DOUBLE_PORT
///////////////////////////////////////////////////////////////////
// Definitions for Display Color
#define DISP_18BIT 0x10 // 18-bit RGB output
#define DISP_24BIT 0x00 // 24-bit RGB output
#define DISP_BIT DISP_18BIT
///////////////////////////////////////////////////////////////////
// Definitions for Display Timing Feature
#define MASK_FIRST_DHS 0x80 // Mask 1st DHS
#define NO_MASKING 0x00 // No masking
#define DHS_MASK NO_MASKING
///////////////////////////////////////////////////////////////////
// Definitions for Display Signal
#define DISP_INV 0x0C // DVS : neg , DHS : neg , DEN : pos
#define DCLK_INV 0x08 // DCLK : pos
#define DCLK_DELAY 0x01 // 1.0ns delay for DCLK
///////////////////////////////////////////////////////////////////
//Definitions for display port control
#define DISP_EO_SWAP 0x00//0x20
#define DISP_RB_SWAP 0x00//0x10
#define DISP_ML_SWAP 0x08
///////////////////////////////////////////////////////////////////
// Definitions for Display Settings
#define MAX_DCLK 138 // Maximum display clock(MHz) that panel can support
#define MAX_RATE 86 // Maximum display refresh rate in Hz that panel can support
#define DH_ACT_STA_POS 0x0020 // DH_ACT_STA_POS should be as small as possible !!!
#define DH_ACT_END_POS 0x0520
#define DV_ACT_STA_POS 0x000c // DV_ACT_STA_POS should be as small as possible !!!
#define DV_ACT_END_POS 0x040c
#define DISP_WID (DH_ACT_END_POS - DH_ACT_STA_POS) // 0x0500 = 1280 pixels
#define DISP_LEN (DV_ACT_END_POS - DV_ACT_STA_POS) // 0x0400 = 1024 lines
#define STD_DH_TOTAL 0x0580 // Standard display clock number in one display horizontal line
#define STD_DV_TOTAL 0x0480 // Standard display horizontal line in one display frame
#define STD_HSYNC_WIDTH 0x10 // Display HSYNC clock width
#define STD_VSYNC_LENGTH 0x03 // Display VSYNC line length
#define MIN_DV_TOTAL 0x0410 // Minimum VSYNC that panel can support
#define FIX_LAST_DHT 0
#define MIN_LAST_DHT 0 // Must set to 0 if you don't care last-line length
#define MAX_LAST_DHT 0
#define VIDEO_ML_DHT 0 // Minimum last-line length for video
#define USER_MODE_NCODE 16 // NEVER change this setting !!!
#define DISP_ALIGN 0 // 0-Left alignment, 1-Right alignment
#define AUTO_SWITCH 0x60 // Auto Switch to freerun mode
/*
///////////////////////////////////////////////////////////////////
// Definitions for RTD3001
#define All_LINE_BUF 0x02 // Turn on all line buffers
#define REQ_DELAY 0x40 // 0.5ns delay for request
#define V_MAC_DELAY 0x10 // 0.5ns delay for Vertical MAC
#define H_MAC_DELAY 0x04 // 0.5ns delay for Horizontal MAC
#define DCLK_DELAY 0x01 // 1.0ns delay for DCLK
#define HINIT_COEFF 0x00 // Horizontal initial coefficient = 0xc000
#define REQMODE_00B 0x00 // Imporved mode 1 : REG[28]-bit3 = 0
#define REQMODE_01B 0x80 // Imporved mode 1 : REG[31]-bit7 = 1
#define ODDCTRL_VGA 0x38 // REG[31]-bit5 : Odd signal for V inital toggle. (0 : inverse)
// REG[31]-bit4 : Odd signal to control FS_DELAY_FINE_TUNING. (0 : enable)
// REG[31]-bit3 : Odd signal to enable FS_DELAY_FINE_TUNING. (1 : inverse)
#define ODDCTRL_VIDEO 0x28
*/
//---------------------------------- 1280x1024 ---------------------------------
///////////////////////////////////////////////////////////////////////////
#ifdef __MAIN__
unsigned char code RTD_PWUP_INI[] =
{
5, Y_INC, HOSTCTRL_02, 0x02,0x00,
4, N_INC, TC_ADDR_PORT_95, 0x00,
7, N_INC, TC_DATA_PORT_96, 0x00,0x00,0x00,0x00,
9, Y_INC, GP1_ODOCTRL_F6, 0x00,0x00,0x00,0x00,0x00,0x00,
6, Y_INC, IRQ_CTRL1_0E, 0x00,0x80,0x00,
4, N_INC, INT_FLD_DETECT_14, 0x00,
25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
6, Y_INC, YUV2RGB_39, 0x00,0x00,0x00,
5, Y_INC, DUTY_FINE_TUNE_3E, 0xc0,0x0e, // For improving display speed
4, N_INC, MEAS_HS_LATCH_4E, 0x00,
5, Y_INC, CLAMP_55, 0x04,0x10,
4, N_INC, COLOR_CTRL_5D, 0x03,
4, N_INC, OP_CRC_CTRL_68, 0x88, // For improving display speed
4, N_INC, OVL_CTRL_6D, 0x02,
4, N_INC, SD_CTRL_70, 0x00,
4, N_INC, FX_LST_LEN_H_5A, 0x00, // Disable fix last line function
6, Y_INC, IVS_DELAY_8C, 0x00,0x00,0x00,
//--------------------------------------------------------------------
// For RSDS TCON START
//--------------------------------------------------------------------
5, Y_INC, TC_ADDR_PORT_95, 0x10,0x0c, // FXDIO TCON1
5, Y_INC, TC_ADDR_PORT_95, 0x11,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x12,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x13,0xa0,
5, Y_INC, TC_ADDR_PORT_95, 0x14,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x15,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x16,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x18,0x0c, // XSTB TCON2
5, Y_INC, TC_ADDR_PORT_95, 0x19,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x1A,0X0c,
5, Y_INC, TC_ADDR_PORT_95, 0x1B,0x35,
5, Y_INC, TC_ADDR_PORT_95, 0x1C,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x1D,0xac,
5, Y_INC, TC_ADDR_PORT_95, 0x1E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x20,0x0c, // YOE TCON3
5, Y_INC, TC_ADDR_PORT_95, 0x21,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x22,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x23,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x24,0x52,
5, Y_INC, TC_ADDR_PORT_95, 0x25,0x14,
5, Y_INC, TC_ADDR_PORT_95, 0x26,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x28,0x0c, // BXDIO TCON4
5, Y_INC, TC_ADDR_PORT_95, 0x29,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x2A,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x2B,0x9f,
5, Y_INC, TC_ADDR_PORT_95, 0x2C,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x2D,0xa9,
5, Y_INC, TC_ADDR_PORT_95, 0x2E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x50,0x0c, // YDIO TCON9
5, Y_INC, TC_ADDR_PORT_95, 0x51,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x52,0x0e,
5, Y_INC, TC_ADDR_PORT_95, 0x53,0xd0,
5, Y_INC, TC_ADDR_PORT_95, 0x54,0x33,
5, Y_INC, TC_ADDR_PORT_95, 0x55,0xd7,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x30,0x0c, // YCLK TCON5
5, Y_INC, TC_ADDR_PORT_95, 0x31,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x32,0X0c,
5, Y_INC, TC_ADDR_PORT_95, 0x33,0xF4,
5, Y_INC, TC_ADDR_PORT_95, 0x34,0x21,
5, Y_INC, TC_ADDR_PORT_95, 0x35,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
#if(ANTI_FLICKER)
5, Y_INC, TC_ADDR_PORT_95, 0x38,0x0c, // POL TCON6
5, Y_INC, TC_ADDR_PORT_95, 0x39,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x3a,0x0E,
5, Y_INC, TC_ADDR_PORT_95, 0x3b,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3c,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3d,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x3e,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0c, // POL TCON7
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0D,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x8C,
#else
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0c, // POL TCON7
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0D,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x88,
#endif
//---------------------------------------------------------------
// For RSDS TCON END
//---------------------------------------------------------------
7, Y_INC, PLL_DIV_CTRL0_C8, 0x04,0x00,0x20,0x18,
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