📄 disp_br1.h
字号:
// 5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0e, // TCON7 : POL
// 5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0f,
// 5, Y_INC, TC_ADDR_PORT_95, 0x43,0xac,
// 5, Y_INC, TC_ADDR_PORT_95, 0x44,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x45,0xad,
// 5, Y_INC, TC_ADDR_PORT_95, 0x46,0x8c,
5, Y_INC, TC_ADDR_PORT_95, 0x08,0x10, // TCON0 : OSTH
5, Y_INC, TC_ADDR_PORT_95, 0x09,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x0a,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x0b,0xa1,//0xa0
5, Y_INC, TC_ADDR_PORT_95, 0x0c,0x22,//0x22
5, Y_INC, TC_ADDR_PORT_95, 0x0d,0xa2,//0xa1
5, Y_INC, TC_ADDR_PORT_95, 0x0e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x10,0x10, // TCON1 : ESTH
5, Y_INC, TC_ADDR_PORT_95, 0x11,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x12,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x13,0xa1,//0xa0
5, Y_INC, TC_ADDR_PORT_95, 0x14,0x22,//0x22
5, Y_INC, TC_ADDR_PORT_95, 0x15,0xa2,//0xa1
5, Y_INC, TC_ADDR_PORT_95, 0x16,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x68,0x11, // TCON12 : GVON
5, Y_INC, TC_ADDR_PORT_95, 0x69,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x6a,0x12,
5, Y_INC, TC_ADDR_PORT_95, 0x6b,0x4d,
5, Y_INC, TC_ADDR_PORT_95, 0x6c,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x6d,0xdd,
5, Y_INC, TC_ADDR_PORT_95, 0x6e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x60,0x11, // TCON11 : GVOFF
5, Y_INC, TC_ADDR_PORT_95, 0x61,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x62,0x12,
5, Y_INC, TC_ADDR_PORT_95, 0x63,0x4d,
5, Y_INC, TC_ADDR_PORT_95, 0x64,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x65,0xdd,
5, Y_INC, TC_ADDR_PORT_95, 0x66,0xC0,
// 5, Y_INC, TC_ADDR_PORT_95, 0x60,0x2f, // TCON11 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x61,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x62,0x30,
// 5, Y_INC, TC_ADDR_PORT_95, 0x63,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x64,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x65,0x10,
// 5, Y_INC, TC_ADDR_PORT_95, 0x66,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x67,0x01, // BLUE
// 5, Y_INC, TC_ADDR_PORT_95, 0x68,0x1f, // TCON12 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x69,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6a,0x20,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6b,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6c,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6d,0x08,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6e,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6f,0x02, // Green
// 5, Y_INC, TC_ADDR_PORT_95, 0x70,0x0f, // TCON13 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x71,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x72,0x10,
// 5, Y_INC, TC_ADDR_PORT_95, 0x73,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x74,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x75,0x01,
// 5, Y_INC, TC_ADDR_PORT_95, 0x76,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x77,0x07, // R & G & B
//////////////////////////////////////////////////////////////////////////
/* //Start Address : 32+640
5, Y_INC, TC_ADDR_PORT_95, 0x50,0x0e, // TCON9 : CKV
5, Y_INC, TC_ADDR_PORT_95, 0x51,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x52,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x53,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x54,0x14,
5, Y_INC, TC_ADDR_PORT_95, 0x55,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0xC0,
5, Y_INC, TC_ADDR_PORT_95, 0x48,0x0f, // TCON8 : OE
5, Y_INC, TC_ADDR_PORT_95, 0x49,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x4a,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x4b,0x65,
5, Y_INC, TC_ADDR_PORT_95, 0x4c,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x4d,0xdd,
5, Y_INC, TC_ADDR_PORT_95, 0x4e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x58,0x0E, // TCON10 : STV
5, Y_INC, TC_ADDR_PORT_95, 0x59,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x5a,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x5b,0x11,
5, Y_INC, TC_ADDR_PORT_95, 0x5c,0x44,
5, Y_INC, TC_ADDR_PORT_95, 0x5d,0x6d,
5, Y_INC, TC_ADDR_PORT_95, 0x5e,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x30,0x0f, // TCON5 : STB
5, Y_INC, TC_ADDR_PORT_95, 0x31,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x32,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x33,0x2d,
5, Y_INC, TC_ADDR_PORT_95, 0x34,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x35,0x35,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
// 5, Y_INC, TC_ADDR_PORT_95, 0x60,0x00, // POL_1
// 5, Y_INC, TC_ADDR_PORT_95, 0x61,0x30,
// 5, Y_INC, TC_ADDR_PORT_95, 0x62,0x0e,
// 5, Y_INC, TC_ADDR_PORT_95, 0x63,0x28,
// 5, Y_INC, TC_ADDR_PORT_95, 0x64,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x65,0x29,
// 5, Y_INC, TC_ADDR_PORT_95, 0x66,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x68,0x00, // POL
// 5, Y_INC, TC_ADDR_PORT_95, 0x69,0x30,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6a,0x0f,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6b,0x2A,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6c,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6d,0x2B,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6e,0x8C,
//One_Line
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0e, // TCON7 : POL
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0f,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0xac,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x44,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0xad,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x88,
//Two_Line
// 5, Y_INC, TC_ADDR_PORT_95, 0x38,0x0c, // TCON6 : POL
// 5, Y_INC, TC_ADDR_PORT_95, 0x39,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x3a,0x0e,
// 5, Y_INC, TC_ADDR_PORT_95, 0x3b,0xaa,
// 5, Y_INC, TC_ADDR_PORT_95, 0x3c,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x3d,0xab,
// 5, Y_INC, TC_ADDR_PORT_95, 0x3e,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0e, // TCON7 : POL
// 5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0f,
// 5, Y_INC, TC_ADDR_PORT_95, 0x43,0xac,
// 5, Y_INC, TC_ADDR_PORT_95, 0x44,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x45,0xad,
// 5, Y_INC, TC_ADDR_PORT_95, 0x46,0x8c,
5, Y_INC, TC_ADDR_PORT_95, 0x08,0x0e, // TCON0 : OSTH
5, Y_INC, TC_ADDR_PORT_95, 0x09,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x0a,0x0f,
5, Y_INC, TC_ADDR_PORT_95, 0x0b,0xa0,
5, Y_INC, TC_ADDR_PORT_95, 0x0c,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x0d,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x0e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x10,0x0e, // TCON1 : ESTH
5, Y_INC, TC_ADDR_PORT_95, 0x11,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x12,0x0f,
5, Y_INC, TC_ADDR_PORT_95, 0x13,0xa0,
5, Y_INC, TC_ADDR_PORT_95, 0x14,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x15,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x16,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x68,0x0f, // TCON12 : GVON
5, Y_INC, TC_ADDR_PORT_95, 0x69,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x6a,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x6b,0x4d,
5, Y_INC, TC_ADDR_PORT_95, 0x6c,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x6d,0xdd,
5, Y_INC, TC_ADDR_PORT_95, 0x6e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x60,0x0f, // TCON11 : GVOFF
5, Y_INC, TC_ADDR_PORT_95, 0x61,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x62,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x63,0x4d,
5, Y_INC, TC_ADDR_PORT_95, 0x64,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x65,0xdd,
5, Y_INC, TC_ADDR_PORT_95, 0x66,0xC0,
// 5, Y_INC, TC_ADDR_PORT_95, 0x60,0x2f, // TCON11 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x61,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x62,0x30,
// 5, Y_INC, TC_ADDR_PORT_95, 0x63,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x64,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x65,0x10,
// 5, Y_INC, TC_ADDR_PORT_95, 0x66,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x67,0x01, // BLUE
// 5, Y_INC, TC_ADDR_PORT_95, 0x68,0x1f, // TCON12 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x69,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6a,0x20,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6b,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6c,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6d,0x08,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6e,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x6f,0x02, // Green
// 5, Y_INC, TC_ADDR_PORT_95, 0x70,0x0f, // TCON13 : Dot Masking
// 5, Y_INC, TC_ADDR_PORT_95, 0x71,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x72,0x10,
// 5, Y_INC, TC_ADDR_PORT_95, 0x73,0x00,
// 5, Y_INC, TC_ADDR_PORT_95, 0x74,0x44,
// 5, Y_INC, TC_ADDR_PORT_95, 0x75,0x01,
// 5, Y_INC, TC_ADDR_PORT_95, 0x76,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x77,0x07, // R & G & B
*/
//---------------------------------------------------------------
// For RSDS TCON END
//---------------------------------------------------------------
9, Y_INC, LVDS_CTRL0_C0, 0x60,0x04,0x52,0x80,0x80,0x68,
4, N_INC, TC_ADDR_PORT_95, 0x00,
4, N_INC, TC_DATA_PORT_96, 0x80,
0
};
// Be Careful !!
// Display window setting in FreeV[] MUST follow the definition of
// 1. DISP_WID and DISP_LEN
// 2. DH_ACT_STA_POS and DH_ACT_END_POS
// 3. DV_ACT_STA_POS and DV_ACT_END_POS
// 4. Background window must be the same as active window.
unsigned char code FreeV[] =
{
27, Y_INC, VDIS_CTRL_20, 0x23 | DISP_BIT | DISPLAY_PORT | DHS_MASK, // Switch to free-run display
DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
(STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8), // DH_TOTAL
STD_HSYNC_WIDTH, // DH_HS_END
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
(STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8), // DV_TOTAL
STD_VSYNC_LENGTH, // DV_VS_END
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
5, Y_INC, FIX_DVTOTAL_LSB_97, (STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8),
#if (NEW_DITHER)
5, Y_INC, FX_LST_LEN_L_59, 0x00,0x98, // Enable fix last line function
#else
5, Y_INC, FX_LST_LEN_L_59, 0x00,0x18, // Enable fix last line function
#endif
4, N_INC, VDIS_CTRL_20, 0x22 | DISP_BIT | DISPLAY_PORT | DHS_MASK, // Disable display timing
4, N_INC, VDIS_CTRL_20, 0x23 | DISP_BIT | DISPLAY_PORT | DHS_MASK, // Restart free-run background
// Force display timing start
6, Y_INC, YUV2RGB_39, 0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
4, N_INC, DIS_TIMING0_3A, 0x00 | DCLK_DELAY,
4, N_INC, INT_FLD_DETECT_14, 0x00,
5, Y_INC, IVS_DELAY_8C, 0x00, 0x00,
4, N_INC, SCALE_CTRL_15, 0x00,
4, N_INC, FILTER_CTRL0_1B, 0xc4,
0
};
unsigned char code OSD_PWUP_INI[] =
{
// PWM Control
5, Y_INC, OSD_ADDR_MSB_90, 0xc0,0x02,
6, N_INC, OSD_DATA_92, 0x03,0x08,0x00,
// PWM Duty Width
5, Y_INC, OSD_ADDR_MSB_90, 0xc0,0x01,
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