📄 frame_sync.lst
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C51 COMPILER V6.20c FRAME_SYNC 04/15/2004 12:59:05 PAGE 1
C51 COMPILER V6.20c, COMPILATION OF MODULE FRAME_SYNC
OBJECT MODULE PLACED IN .\Output\Frame_Sync.obj
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE Code\Frame_Sync.c OPTIMIZE(9,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Outpu
-t\Frame_Sync.lst) OBJECT(.\Output\Frame_Sync.obj)
stmt level source
1 #define __FRAMESYNC__
2
3 #include "Header\Frame_Sync.h"
4 #include "Header\Lcd_func.h"
5 #include "Header\Access.h"
6 #include "Header\Main_def.h"
7 #include "Header\Config.h"
8 #include "Header\Lcd_main.h"
9 #include "Header\LCD_OSD.h"
10
11
12 /////////////////////////
13 // Frame-Sync Detector //
14 /////////////////////////
15 bit Frame_Sync_Detector(void)
16 {
17 1 if (bPower_Status && bStable && MODE_NOSIGNAL != ucMode_Curr && MODE_NOSUPPORT != ucMode_Curr)
18 1 {
19 2 if (bFrameSync)
20 2 {
21 3 RTDRead(STATUS0_01, 1, N_INC); // Read Status
22 3
23 3 if (0x00 == (Data[0] & 0x03))
24 3 {
25 4 // No event occurred. Just return 0
26 4 if (SOURCE_VGA != (stGUD1.INPUT_SOURCE & 0x07)) return _FALSE;
27 4
28 4 if (0x00 == (Data[0] & 0x80))
29 4 {
30 5 #if (TUNE_APLL)
31 5 if (0 == ucPE_Level)
32 5 {
33 6 RTDSetBit(DV_TOTAL_STATUS_3D, 0x7f, 0x20); //Enable PE Max Measurement
34 6 Delay_Xms(1);
35 6 RTDRead(DV_TOTAL_STATUS_3D, 1, N_INC); //Read PE Max
36 6
37 6 if (0x10 < (Data[0] & 0x1f))
38 6 {
39 7 ucPE_Level = 1;
40 7 Adjust_I_Code();
41 7
42 7 if (ucI_Code & 0x80)
43 7 RTDSetBit(I_CODE_MB_CA, 0xdf, 0x20); //Set the I_Code[13] to 1;
44 7 else
45 7 RTDSetBit(I_CODE_MB_CA, 0xdf, 0x00); //Set the I_Code[13] to 0;
46 7
47 7 ucI_Code = ucI_Code & 0x7f;
48 7 RTDSetByte(I_CODE_LB_C9, 0x1c | ((ucI_Code & 0x07) << 5));
49 7 RTDSetBit(I_CODE_MB_CA, 0xfc, 0x04 | ((ucI_Code & 0x18) >> 3));
50 7
51 7 RTDSetBit(DV_TOTAL_STATUS_3D, 0xdf, 0x00); //Disable PE Max Measurement
52 7 RTDSetByte(DV_TOTAL_STATUS_3D, 0x40); //Clear PE Max value
53 7 }
54 6 }
C51 COMPILER V6.20c FRAME_SYNC 04/15/2004 12:59:05 PAGE 2
55 5 #endif
56 5 // No event occurred. Just return 0
57 5 return _FALSE;
58 5 }
59 4 }
60 3
61 3 // You will reach here only when :
62 3 // 1. Underflow / Overflow occurred.
63 3 // 2. PLL mislock for VGA source.
64 3 // Return 1 will cause display to reset.
65 3 Reset_Mode();
66 3
67 3 return _TRUE;
68 3 }
69 2 else
70 2 {
71 3 RTDRead(VDIS_CTRL_20, 1, N_INC);
72 3
73 3 if (0 == (Data[0] & 0x08))
74 3 {
75 4 // You will reach here only when input format change during
76 4 // Display_VGA_Set()/Display_DVI_Set and Set_Panel(), and
77 4 // watch-dog change display to free-run mode.
78 4 Reset_Mode();
79 4 return _TRUE;
80 4 }
81 3 }
82 2 }
83 1
84 1 // No event occurred. Just return 0
85 1 return _FALSE;
86 1 }
87
88 /////////////////////////////////////////////////////////////////////////////////
89 // FrameSync fine-tune routines
90 /////////////////////////////////////////////////////////////////////////////////
91
92 unsigned char TestSync(unsigned int offset) // 0 - Success; Otherwise - Fail
93 {
94 1 // Apply DCLK frequency setting
95 1 RTDSetByte(DCLK_OFFSET_LSB_9A, (unsigned char)offset);
96 1 RTDSetBit(DCLK_OFFSET_MSB_9B, 0xf0, (unsigned char)((offset >> 8) & 0x0f) | 0x20);
97 1
98 1 Wait_For_Event(EVENT_DVS); // Wait for Frame End
99 1
100 1 RTDSetByte(STATUS0_01, 0x00); // Clear Status
101 1
102 1 Wait_For_Event(EVENT_DVS); // Wait for Frame End
103 1 Wait_For_Event(EVENT_DVS); // Wait for Frame End
104 1
105 1 RTDRead(STATUS0_01, 1, N_INC); // Read status
106 1
107 1 if (Data[0])
108 1 RTDSetByte(STATUS0_01, 0x00); // Clear Status
109 1
110 1 // Input timing changed.
111 1 if (Data[0] & 0x60) return 1;
112 1
113 1 // Save underflow/overflow information into Data[0]
114 1 Data[0] &= 0x03;
115 1
116 1 return 0; // Success
C51 COMPILER V6.20c FRAME_SYNC 04/15/2004 12:59:05 PAGE 3
117 1 }
118
119
120
121
122 // Issac :
123 // Offset_Step is the DCLK frequency step for searching frame-sync.
124 #define Offset_Step 32
125
126 //Returned value
127 // 0 : Succeed
128 // 1 : Fail
129 // 2 : Abort
130
131 unsigned char Frame_Sync(void)
132 {
133 1 unsigned int usBuffer, usDelta;
134 1 unsigned char ucFine;
135 1
136 1 #if (FIX_LAST_DHT)
unsigned int usMax_Last_Line, usMin_Last_Line;
#endif
139 1
140 1 //Disable the Fixed DVTOTAL & Last Line Length Fucntion
141 1 RTDSetBit(FX_LST_LEN_H_5A, 0xef, 0x08);
142 1
143 1 //Disable spread spectrum
144 1 RTDSetBit(SPREAD_SPECTRUM_99, 0x0f, 0x00);
145 1 RTDSetBit(DCLK_OFFSET_MSB_9B, 0xff, 0x20);
146 1
147 1 //Read the DCLK offset
148 1 RTDRead(DCLK_OFFSET_LSB_9A, 2, Y_INC);
149 1 Data[2] = Data[1] & 0x0f;
150 1 Data[3] = Data[0];
151 1 usBuffer = ((unsigned int*)Data)[1];
152 1
153 1 if ((SOURCE_VGA == (stGUD1.INPUT_SOURCE & 0x07)) || (SOURCE_DVI == (stGUD1.INPUT_SOURCE & 0x07)))
154 1 {
155 2 // Issac :
156 2 // In order to enable full-scale spread spectrum, offset value must be within 30%~70% (1228~2866)
157 2 while (usBuffer < (1228 + 16 * Offset_Step))
158 2 {
159 3 RTDRead(DPLL_M_D1, 2, Y_INC);
160 3 RTDSetByte(DPLL_M_D1, Data[0] + 1);
161 3 RTDSetByte(DPLL_N_D2, Data[1]);
162 3
163 3 // Forster :
164 3 // If the DCLK offset too small, then set the M_Code = M_Code + 1 and reculculate the offset
165 3 // Original formula:
166 3 // 24.576MHz * (M/N) * (1 - Old_Offset / 2^15) = 24.576MHz * (M+1)/N * (1 - (New_Offset /2^15)
-)
167 3 // => New_Offset = (2^15 + (M*Old_Offset)) / (M+1);
168 3 usBuffer = (unsigned int)((unsigned long)(32768 + (unsigned long)(Data[0] + 2) * usBuffer)
-/ (unsigned long)(Data[0] + 3));
169 3 }
170 2 }
171 1
172 1 usDelta = 0x03;
173 1 ucFine = 0x0f;
174 1 do
175 1 {
176 2 if (TestSync(usBuffer)) return 2;
C51 COMPILER V6.20c FRAME_SYNC 04/15/2004 12:59:05 PAGE 4
177 2
178 2 if (0 == Data[0]) break;
179 2
180 2 if (Data[0] & 0x02)
181 2 usBuffer -= (usDelta & 0x01) ? (Offset_Step / 2) : Offset_Step;
182 2 else
183 2 usBuffer += (usDelta & 0x02) ? (Offset_Step / 2) : Offset_Step;
184 2
185 2 usDelta = Data[0];
186 2 }
187 1 while (--ucFine);
188 1
189 1 if (0x00 == ucFine) return 1;
190 1
191 1 if (TestSync(usBuffer - 4)) return 2;
192 1
193 1 //usDelta = Data[0] ? usBuffer + 2 : usBuffer - 2;
194 1
195 1 if (Data[0])
196 1 {
197 2 if (TestSync(usBuffer + 4)) return 2;
198 2
199 2 usDelta = Data[0] ? usBuffer : usBuffer + 2;
200 2 }
201 1 else
202 1 {
203 2 if (TestSync(usBuffer + 4)) return 2;
204 2
205 2 usDelta = Data[0] ? usBuffer - 2 : usBuffer;
206 2 }
207 1
208 1 if (TestSync(usDelta)) return 2;
209 1
210 1 if (Data[0])
211 1 {
212 2 usDelta = usBuffer;
213 2
214 2 if (TestSync(usDelta)) return 2;
215 2 }
216 1
217 1 // Save safe DCLK offset for frame-sync
218 1 usBuffer = usDelta;
219 1
220 1 #if (FIX_LAST_DHT == 0)
221 1
222 1 #if (SPREAD_SPECTRUM)
223 1
224 1 //Enable the spread spectrum function
225 1 RTDSetBit(SPREAD_SPECTRUM_99, 0x00, (DCLK_SPREAD_RANGE << 4));
226 1 RTDSetBit(DCLK_OFFSET_MSB_9B, 0xff, 0x20);
227 1
228 1 usDelta = usDelta + DCLK_OFFSET[DCLK_SPREAD_RANGE];
229 1
230 1 if (TestSync(usDelta)) return 2;
231 1
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