📄 mode_detect.lst
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// Check field rate
if (Data[0] & 0x40)
{
ucMode_Curr = MODE_NOSIGNAL;
}
else
{
if (ucAV_Mode & 0x02) // 50Hz
{
if (0x00 != (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
else // 60Hz
{
if (0x00 == (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
}
// Check result
if (MODE_NOSIGNAL == ucMode_Curr)
Reset_Mode();
else
bStable = 1; // Set bStable to 1 when signal timing is stable.
}
#endif
1075
1076
1077
1078
1079 void Calculate_IVS2DVS_Delay(unsigned char integer, unsigned char fraction, unsigned int DVStart)
1080 {
1081 1 if ((usIPV_ACT_STA + integer) < (DVStart >> 6))
1082 1 {
1083 2 // You should never get into this code ....
1084 2 usIPV_ACT_STA = ( DVStart >> 6) - integer;
1085 2
1086 2 RTDSetByte(IPV_ACT_STA_0A, (unsigned char)usIPV_ACT_STA);
1087 2 RTDSetByte(IPV_ACT_STA_0A + 1, (unsigned char)(usIPV_ACT_STA >> 8));
1088 2 }
1089 1
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 19
1090 1 ((unsigned int *)Data)[0] = ((usIPV_ACT_STA + integer) << 6) + ((unsigned int)fraction << 6) / 10 - DV
-Start;
1091 1
1092 1 ucDV_Delay = (unsigned char)(((unsigned int*)Data)[0] >> 6);
1093 1
1094 1 Data[6] = ((unsigned int*)Data)[0] - (ucDV_Delay << 6);
1095 1 Data[6] = (unsigned long)usADC_Clock * Data[6] / 1024;
1096 1
1097 1 RTDSetByte(FS_FT_DELAY_1E, Data[6]);
1098 1 RTDSetByte(IV_DV_LINES_38, ucDV_Delay);
1099 1 }
1100
1101 void Set_Dclk(unsigned int DispLen)
1102 {
1103 1 ((unsigned int *)Data)[0] = (unsigned long)8 * usDH_Total * USER_MODE_NCODE * DispLen
1104 1 / ((unsigned long)usIPV_ACT_LEN * usHsync);
1105 1
1106 1 //Original Formula : DPM/Ich = 17.6 must be constant
1107 1 //Ich = DPM * 10 / 176
1108 1 //2*Ich = DPM * 20 / 176 , set D0[0] to 0, then I = 2 * Ich
1109 1 //I = 2 * Ich = 2.5u + D0[3]*2.5u + D0[4]*5u + D0[5]*10u + D0[6]*20u + D0[7]*30u(A)
1110 1 //2I = 4 * Ich = 5u + D0[3]*5u + D0[4]*10u + D0[5]*20u + D0[6]*40u + D0[7]*60u(A)
1111 1
1112 1 Data[15] = ((unsigned int *)Data)[0] >> 2;
1113 1 Data[5] = (unsigned int)Data[15] * 40 / 176 - 5; //Calculate the 4*Ich,
1114 1 Data[6] = 0x00;
1115 1
1116 1 if (Data[5] > 60)
1117 1 {
1118 2 Data[5] -= 60;
1119 2 Data[6] |= 0x80;
1120 2 }
1121 1
1122 1 if (Data[5] > 40)
1123 1 {
1124 2 Data[5] -= 40;
1125 2 Data[6] |= 0x40;
1126 2 }
1127 1
1128 1 if (Data[5] > 20)
1129 1 {
1130 2 Data[5] -= 20;
1131 2 Data[6] |= 0x20;
1132 2 }
1133 1
1134 1 if (Data[5] > 10)
1135 1 {
1136 2 Data[5] -= 10;
1137 2 Data[6] |= 0x10;
1138 2 }
1139 1
1140 1 if (Data[5] > 5)
1141 1 {
1142 2 Data[5] -= 5;
1143 2 Data[6] |= 0x08;
1144 2 }
1145 1
1146 1 Data[0] = 7;
1147 1 Data[1] = Y_INC;
1148 1 Data[2] = DPLL_CTRL_D0;
1149 1 Data[3] = Data[6];
1150 1 Data[4] = Data[15] + 1 - 2; //(Data[15] + 1 - 2)
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 20
1151 1 Data[5] = 0x30 | (USER_MODE_NCODE - 2); //Enable SSP and Offset Frequency Direction set to Downward
1152 1 Data[6] = 0x04;
1153 1 Data[7] = 0;
1154 1 RTDWrite(Data);
1155 1
1156 1 //More precise Dclk in KHz
1157 1 ((unsigned long*)Data)[0] = ((unsigned long)RTD_XTAL * 1000) / usIPV_ACT_LEN * DispLen / usHsync * usD
-H_Total ;
1158 1 //Set M/N code Dclk
1159 1 ((unsigned long*)Data)[1] = ((unsigned long)RTD_XTAL * 1000 / 2) * (Data[15] + 1) / USER_MODE_NCODE;
1160 1
1161 1
1162 1 ((unsigned long*)Data)[2] = ((unsigned long*)Data)[1] - ((unsigned long*)Data)[0]; //Dclk offset
1163 1 ((unsigned long*)Data)[3] = ((unsigned long*)Data)[1] >> 15; //Offset resolution equal to (Dclk / 2^15
-)
1164 1
1165 1 ((unsigned long*)Data)[3] = ((((unsigned long*)Data)[2] << 1) / ((unsigned long*)Data)[3]) & 0x00000ff
-f; //Calculate the Dclk offset
1166 1
1167 1 RTDSetByte(DCLK_OFFSET_LSB_9A, (unsigned char)((unsigned long*)Data)[3]); //Set the Dclk offset
1168 1 RTDSetBit(DCLK_OFFSET_MSB_9B, 0xf0, (unsigned char)(((unsigned long*)Data)[3] >> 8) | 0x20);
1169 1
1170 1 RTDSetBit(FX_LST_LEN_H_5A, 0xff, 0x08); //Enable DDS Spread Spectrum Output Function
1171 1
1172 1 /*
1173 1 RTDSetBit(DPLL_N_D2,0xff,0x20); //DPLL Spread Spectrum Enable
1174 1 RTDSetBit(DPLL_FILTER_D3,0x7f,0x00); //Enable DPll output
1175 1 */
1176 1 }
1177
1178 void Initial_Mode(void)
1179 {
1180 1 unsigned char ucOption, ucDelay;
1181 1 unsigned int usDispLen;
1182 1
1183 1
1184 1 // bit 7 of ucMode_Curr : partial-V display.
1185 1 // bit 6 of ucMode_Curr : select 720x350 or 720x400 for VGA-50Hz and VGA-60Hz
1186 1 ucOption = ucMode_Curr & 0xc0;
1187 1 ucMode_Curr = ucMode_Curr & 0x3f;
1188 1
1189 1 RTDSetBit(SD_CTRL_70, 0xf9, VGA_ICLK_DELAY);
1190 1
1191 1 if (SOURCE_DVI == (stGUD1.INPUT_SOURCE & 0x07))
1192 1 {
1193 2 RTDSetBit(SD_CTRL_70, 0xf9, TMDS_ICLK_DELAY);
1194 2
1195 2 usIPH_ACT_STA = CAP_WIN[ucMode_Curr][1];
1196 2 }
1197 1 else
1198 1 {
1199 2 if (ucOption & 0x40)
1200 2 {
1201 3 // Only VGA-50Hz and VGA-60Hz mode will set bit 6 of ucMode_Curr to indicate 720-pixel capture
- width
1202 3 // In these case, we should use 720 horizontal settings instead of 640 horizontal settings in
-table.
1203 3 usADC_Clock = CAP_WIN[MODE_0720x0400x70HZ][0];
1204 3 usIPH_ACT_STA = CAP_WIN[MODE_0720x0400x70HZ][1];
1205 3 usIPH_ACT_WID = CAP_WIN[MODE_0720x0400x70HZ][2];
1206 3 }
1207 2 else
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 21
1208 2 {
1209 3 usADC_Clock = CAP_WIN[ucMode_Curr][0];
1210 3 usIPH_ACT_STA = CAP_WIN[ucMode_Curr][1];
1211 3 usIPH_ACT_WID = CAP_WIN[ucMode_Curr][2];
1212 3
1213 3 // Calculate pixel clock rate (round to MHz)
1214 3 usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
1215 3 usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
1216 3
1217 3 // Use ADC to do H scale-down if pixel clock rate is over spec.
1218 3 if (MAX_ADC_FREQ < usDispLen && MODE_USER1152x864 <= ucMode_Curr && MODE_USER1600x1200 >= ucMo
-de_Curr)
1219 3 {
1220 4 usADC_Clock = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][0];
1221 4 usIPH_ACT_STA = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][1];
1222 4 usIPH_ACT_WID = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][2];
1223 4 }
1224 3 } //if (ucOption & 0x40)
1225 2
1226 2 // Calculate pixel clock rate (round to MHz)
1227 2 usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
1228 2 usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
1229 2
1230 2 // To improve ADC performance ,when the data rate is slow, use single channel,otherwise, use dual
-channel
1231 2 RTDSetBit(ADC_REG_CLK_EA,0xe0,(45 > usDispLen) ? 0x10 | (ADC_RED_PHASE_FT & 0x0c) |( ADC_BLUE_PHAS
-E_FT & 0x03)
1232 2 : 0x00 | (ADC_RED_PHASE_FT & 0x0c) |( ADC_BLUE_PHASE_FT & 0x03));
1233 2
1234 2 // To imporve the FIFO efficiency only when input data rate is slow, and display data rate is high
-.
1235 2 // RTDSetBit(VGIP_CTRL_04, 0xe3, (40 > usDispLen) ? 0x14 : 0x00);
1236 2 RTDSetBit(VGIP_CTRL_04, 0xf3, (60 > usDispLen) ? 0x08 : 0x00);
1237 2
1238 2 // Set ADC bandwidth to reduce high frequency noise
1239 2 RTDSetByte(ADC_REG_TEST_E9, (68 > usDispLen) ? 0x08 : 0x10);
1240 2
1241 2 RTDSetByte(PE_CONTROL_3C, 0x00); // HSYNC positive/negtive tracking
1242 2
1243 2 #if (ADC_DEFFERENTIAL)
1244 2 RTDSetBit(ADC_DIFF_MODE_EC,0xff,0x40); // Differential mode
1245 2 #else
RTDSetBit(ADC_DIFF_MODE_EC,0xbf,0x00); // Single endded mode
#endif
1248 2 // Fine-tune R/G/B delay
1249 2 RTDSetByte(ADC_REG_CUR_H_E8, 0x0d | (ADC_GREEN_PHASE_FT & 0x30));
1250 2 RTDSetBit(ADC_FRAME_MODULE_EB, 0xc7,
1251 2 ((ADC_RED_PHASE_FT & 0x10) << 1) | ((ADC_GREEN_PHASE_FT & 0x40) << 2) |((ADC_BLUE_PHASE_FT & 0
-x04) << 1));
1252 2
1253 2 // Enable the ADC frame-modulation and digital filter
1254 2 RTDSetByte(ADC_FRAME_MODULE_EB, 0x06);
1255 2 RTDSetBit(TMDS_CORRECTION_FF, 0xff, 0x04);
1256 2
1257 2 // Get usIPV_ACT_LEN
1258 2 if (MODE_UNDEFINED0 > ucMode_Curr)
1259 2 {
1260 3 // We've already decided usIPV_ACT_LEN in Detect_VGA_Mode() for undefined SU/SD mode.
1261 3 // Only defined modes need to decide usIPV_ACT_LEN here.
1262 3 usIPV_ACT_LEN = CAP_WIN[ucMode_Curr][4];
1263 3 }
1264 2
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 22
1265 2 } //if (SOURCE_DVI == (stGUD1.INPUT_SOURCE & 0x07))
1266 1
1267 1 // Get standard usIPV_ACT_STA
1268 1 RTDSetByte(IVS_DELAY_8C, PROGRAM_VDELAY);
1269 1 usIPV_ACT_STA = CAP_WIN[ucMode_Curr][3] - PROGRAM_VDELAY - 1;
1270 1
1271 1 RTDSetByte(IHS_DELAY_8D, PROGRAM_HDELAY);
1272 1
1273 1 if (MODE_0800x0600x75HZ > ucMode_Curr)
1274 1 Data[0] = 2;
1275 1 else if (MODE_1280x1024x75HZ > ucMode_Curr)
1276 1 Data[0] = 5;
1277 1 else
1278 1 Data[0] = 3;
1279 1
1280 1 // usIPH_ACT_STA = usIPH_ACT_STA + CAPTURE_HDELAY - PROGRAM_HDELAY;
1281 1 usIPH_ACT_STA = usIPH_ACT_STA + Data[0] - PROGRAM_HDELAY;
1282 1
1283 1 // Decide display length (height) and store to usDispLen
1284 1
1285 1 usDispLen = Mode_Preset[ucMode_Curr][2];
1286 1
1287 1 // For partial display
1288 1 if (MODE_UNDEFINED0 == ucMode_Curr) // partical-screen scale-up mode
1289 1 {
1290 2 if (ucOption & 0x80) // partial-V
1291 2 {
1292 3 if (MIN_DV_TOTAL > (usVsync - 1))
1293 3 usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
1294 3 else
1295 3 usDispLen = usIPV_ACT_LEN; // No V scale-up
1296 3 }
1297 2 }
1298 1 else if (MODE_UNDEFINED1 == ucMode_Curr) // partial-screen scale-down mode
1299 1 {
1300 2 if (ucOption & 0x80) // partial-V
1301 2 {
1302 3 usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
1303 3 }
1304 2 }
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