📄 mode_detect.lst
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/ ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
if (MAX_DCLK < ((unsigned int *)Data)[0])
{
// If clock rate for full-screen display is too high, we can try partial-V display.
// Estimate clock for partial-V display
// DCLK = (XTAL / usHsync) * DCLK per display line * (min. display total lines / input total l
-ines)
((unsigned int *)Data)[1] = (unsigned long)(RTD_XTAL / 10) * Mode_Preset[MODE_UNDEFINED1][0]
- * MIN_DV_TOTAL
/ ((unsigned long)100 * (usVsync - 1) * usHsync);
if (MAX_DCLK < ((unsigned int *)Data)[1])
{
// Decrease usIPV_ACT_LEN to DISP_LEN and go further to check if it can be displayed.
usIPV_ACT_LEN = DISP_LEN;
}
else
{
ucMode_Temp = MODE_UNDEFINED1 | 0x80; // Scale-down and partial-V display
}
}
else
ucMode_Temp = MODE_UNDEFINED1; // Scale-down and full-V display
}
if (DISP_LEN >= usIPV_ACT_LEN) // V Scale-up
{
((unsigned int *)Data)[0] = (unsigned long)(RTD_XTAL / 10) * Mode_Preset[MODE_UNDEFINED0][0] * D
-ISP_LEN
/ ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
if (MAX_DCLK < ((unsigned int *)Data)[0])
{
if (MIN_DV_TOTAL >= (usVsync - 1))
{
((unsigned int *)Data)[1] = (unsigned long)(RTD_XTAL / 10) * Mode_Preset[MODE_UNDEFINED0
-][0]
* MIN_DV_TOTAL / ((unsigned long)100 * (usVsync - 1) * usHsync
-);
}
else
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 6
{
((unsigned int *)Data)[1] = (unsigned long)(RTD_XTAL / 10) * Mode_Preset[MODE_UNDEFINED0
-][0]
/ ((unsigned long)100 * usHsync);
}
if (MAX_DCLK < ((unsigned int *)Data)[1])
ucMode_Temp = MODE_NOSUPPORT; // Cannot display
else
ucMode_Temp = MODE_UNDEFINED0 | 0x80; // Scale-up and partial-V display
}
else
ucMode_Temp = MODE_UNDEFINED0; // Scale-up and full-V display
}
return ucMode_Temp;
}
#endif
313
314
315
316 void Sync_Type_Switch(void)
317 {
318 1 if (MODE_NOSIGNAL == ucMode_Curr)
319 1 {
320 2 bVpole_Curr = 1;
321 2 bHpole_Curr = 1;
322 2
323 2 switch (ucSync_Type)
324 2 {
325 3 case SYNC_SS : // SS->SOG
326 3 RTDCodeW(VGA_SET_SOG);
327 3 ucSync_Type = SYNC_SOG;
328 3 break;
329 3 case SYNC_CS : // CS->SS
330 3 RTDCodeW(VGA_SET_SS);
331 3 ucSync_Type = SYNC_SS;
332 3 break;
333 3 default : // SOG->CS
334 3 RTDCodeW(VGA_SET_CS);
335 3 ucSync_Type = SYNC_CS;
336 3 break;
337 3 }
338 2 }
339 1 }
340
341 void Sync_Type_Confirm(void)
342 {
343 1 //#if (SOURCE_AUTO_SCAN == _FALSE)
344 1
345 1 unsigned char m;
346 1
347 1 if (SYNC_SS == ucSync_Type)
348 1 {
349 2 // To prevent from mistaking CS (with VS) for SS, we check SYNC type once when finding a mode in S
-S.
350 2
351 2 RTDSetByte(SYNC_CTRL_4B, 0x55);
352 2 RTDSetByte(SYNC_POR_4C, 0x22);
353 2
354 2 m = (MODE_DETECT_FREQ + 1) * 20;
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 7
355 2 do
356 2 {
357 3 Delay_Xms(1);
358 3 RTDRead(SYNC_POR_4C, 0x05, Y_INC);
359 3 }
360 2 while ((Data[0] & 0x02) && (--m));
361 2
362 2 Data[5] = Data[3];
363 2 Data[4] = Data[4] & 0x87;
364 2 Data[3] = Data[1];
365 2 Data[2] = Data[2] & 0x8f;
366 2
367 2 if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
368 2 (0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
369 2 (0 == m))
370 2 {
371 3 ucSync_Type = SYNC_SS;
372 3
373 3 RTDSetByte(SYNC_CTRL_4B, 0x14);
374 3 }
375 2 else
376 2 {
377 3 ucSync_Type = SYNC_CS;
378 3
379 3 RTDCodeW(VGA_SET_CS);
380 3
381 3 bVpole_Curr = 1;
382 3 bHpole_Curr = 1;
383 3 }
384 2 }
385 1 else if (SYNC_SOG == ucSync_Type)
386 1 {
387 2 // Issac :
388 2 // We ignore SOG if SYNC signal is available, because SOG is not good for phase and noise
389 2
390 2 RTDSetByte(SYNC_CTRL_4B, 0x14);
391 2 Delay_Xms(8);
392 2
393 2 RTDSetByte(SYNC_POR_4C, 0x00);
394 2 RTDSetByte(SYNC_POR_4C, 0x02);
395 2
396 2 m = (MODE_DETECT_FREQ + 1) * 20;
397 2 do
398 2 {
399 3 Delay_Xms(1);
400 3 RTDRead(SYNC_POR_4C, 0x05, Y_INC);
401 3 }
402 2 while ((Data[0] & 0x02) && (--m));
403 2
404 2 Data[5] = Data[3];
405 2 Data[4] = Data[4] & 0x87;
406 2 Data[3] = Data[1];
407 2 Data[2] = Data[2] & 0x8f;
408 2
409 2 if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
410 2 (0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
411 2 (0 == m))
412 2 {
413 3 ucSync_Type = SYNC_SOG;
414 3
415 3 RTDSetByte(SYNC_CTRL_4B, 0x57);
416 3 Delay_Xms(8);
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 8
417 3
418 3 RTDSetByte(SYNC_POR_4C, 0x22);
419 3 Delay_Xms(20);
420 3 RTDSetByte(SYNC_POR_4C, 0x00);
421 3 }
422 2 else
423 2 {
424 3 ucSync_Type = SYNC_SS;
425 3
426 3 RTDCodeW(VGA_SET_SS);
427 3
428 3 bVpole_Curr = 1;
429 3 bHpole_Curr = 1;
430 3 }
431 2 }
432 1 //#endif
433 1 }
434
435
436 /////////////////////////////////////////////////////////
437 //------------ Detect VGA & DVI Mode ----------------//
438 /////////////////////////////////////////////////////////
439 void Detect_Input_Mode(void)
440 {
441 1 unsigned char ucMode_Temp;
442 1 unsigned int usHS_Pulse;
443 1
444 1 RTDRead(SYNC_POR_4C, 0x09, Y_INC);
445 1
446 1 if (Data[0] & 0x02)
447 1 {
448 2 // Reset Sync Processor when sync signal timeout
449 2 RTDSetByte(SYNC_POR_4C, SOURCE_VGA == (stGUD1.INPUT_SOURCE & 0x07) ? 0x20 : 0x00);
450 2
451 2 // Treat sync signal timeout as no signal
452 2 ucMode_Temp = MODE_NOSIGNAL;
453 2 }
454 1 else
455 1 {
456 2 usStdHS = usHsync; // Save previous usHsync in usStdHS
457 2 usStdVS = usVsync; // Save previous usVsync in usStdVS
458 2
459 2 bVpole_Curr = (bit)(Data[0] & 0x08); // Save current usVsync polarity
460 2 bHpole_Curr = (bit)(Data[0] & 0x04); // Save current usHsync polarity
461 2
462 2 Data[7] = Data[5];
463 2 Data[6] = Data[6] & 0x0f;
464 2 Data[5] = Data[3];
465 2 Data[4] = Data[4] & 0x87;
466 2 Data[3] = Data[1];
467 2 Data[2] = Data[2] & 0x8f;
468 2
469 2 usHsync = ((unsigned int *)Data)[1]; // Current HSYNC timing
470 2 usVsync = ((unsigned int *)Data)[2]; // Current VSYNC timing
471 2 usHS_Pulse = ((unsigned int *)Data)[3]; // Current HSYNC pulse width
472 2
473 2 // Calculate Vertical Refresh Rate
474 2 // Original Formula :
475 2 // ucRefresh = XTAL / (usHsync * usVsync)
476 2 // Use Data[0~3] as a temporary long variable
477 2 ((unsigned long *)Data)[0] = (unsigned long)usHsync * usVsync;
478 2
C51 COMPILER V6.20c MODE_DETECT 04/15/2004 12:59:19 PAGE 9
479 2 ucRefresh = ((unsigned long)RTD_XTAL * 1000 * 2) / ((unsigned long *)Data)[0];
480 2
481 2 ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
482 2
483 2 // Treat small change of usHsync/usVsync as no change
484 2 if (usStdHS <= usHsync && (usStdHS + 2) >= usHsync) usHsync = usStdHS;
485 2 if (usStdVS <= usVsync && (usStdVS + 2) >= usVsync) usVsync = usStdVS;
486 2
487 2 // If HSYNC/VSYNC polarity changed, we have to update sync-processor setting
488 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
489 2 {
490 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
491 3
492 3 if (SOURCE_VGA == (stGUD1.INPUT_SOURCE & 0x07))
493 3 {
494 4 Data[0] &= 0xd7; // HS_RAW & VS positive
495 4
496 4 if (!bHpole_Curr) Data[0] |= 0x20;
497 4
498 4 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
499 4
500 4 ucMode_Temp = MODE_NOSUPPORT;
501 4 }
502 3 else // if ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
503 3 {
504 4 Data[0] &= 0xf3; // VS & HS positive
505 4
506 4 if (!bHpole_Curr) Data[0] |= 0x04;
507 4 if (!bVpole_Curr) Data[0] |= 0x08;
508 4 }
509 3
510 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
511 3 }
512 2 else
513 2 {
514 3 // There is no change on HSYNC/VSYNC polarity ....
515 3
516 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
517 3 {
518 4 // Treat HSYNC/VSYNC overflow as no signal
519 4 ucMode_Temp = MODE_NOSIGNAL;
520 4
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