clock.drc

《Protel DXP 2004 SP2原理图与PCB设计（第2版）》范例源文件

Protel Design System Design Rule Check
PCB File : \chart14\clock\Clock.PcbDoc
Date     : 2010-8-5
Time     : 10:28:50

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
   Violation between Pad R1-7(139.473mm,103.531mm)  Top Layer and 
                     Pad R1-8(139.473mm,102.881mm)  Top Layer   
   Violation between Pad R1-6(139.473mm,104.181mm)  Top Layer and 
                     Pad R1-7(139.473mm,103.531mm)  Top Layer   
   Violation between Pad R1-5(139.473mm,104.831mm)  Top Layer and 
                     Pad R1-6(139.473mm,104.181mm)  Top Layer   
   Violation between Pad R1-4(139.473mm,105.481mm)  Top Layer and 
                     Pad R1-5(139.473mm,104.831mm)  Top Layer   
   Violation between Pad R1-3(139.473mm,106.131mm)  Top Layer and 
                     Pad R1-4(139.473mm,105.481mm)  Top Layer   
   Violation between Pad R1-2(139.473mm,106.781mm)  Top Layer and 
                     Pad R1-3(139.473mm,106.131mm)  Top Layer   
   Violation between Pad R1-1(139.473mm,107.431mm)  Top Layer and 
                     Pad R1-2(139.473mm,106.781mm)  Top Layer   
   Violation between Track (67.945mm,40.894mm)(120.269mm,40.894mm)  Bottom Layer and 
                     Track (67.1576mm,40.767mm)(68.0466mm,41.656mm)  Bottom Layer   
Rule Violations :8

Processing Rule : Broken-Net Constraint ( (All) )
   Violation         Net D6   is broken into 2 sub-nets. Routed To 50.00%
     Subnet : U3-33    U2-10    
     Subnet : U1-18    
   Violation         Net D7   is broken into 2 sub-nets. Routed To 50.00%
     Subnet : U3-32    U2-11    
     Subnet : U1-19    
   Violation         Net DP   is broken into 2 sub-nets. Routed To 85.71%
     Subnet : DS6-7    DS5-7    DS4-7    DS3-7    DS2-7    DS1-7    R1-8     
     Subnet : U1-21    
   Violation         Net F   is broken into 2 sub-nets. Routed To 85.71%
     Subnet : DS6-2    DS5-2    DS4-2    DS3-2    DS2-2    DS1-2    R1-6     
     Subnet : U1-23    
   Violation         Net G   is broken into 2 sub-nets. Routed To 85.71%
     Subnet : DS6-3    DS5-3    DS4-3    DS3-3    DS2-3    DS1-3    R1-7     
     Subnet : U1-22    
Rule Violations :5

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0


Violations Detected : 13
Time Elapsed        : 00:00:00