pcb1.drc

《Protel DXP 2004 SP2原理图与PCB设计（第2版）》范例源文件

Protel Design System Design Rule Check
PCB File : \chart14\clock\PCB1.PcbDoc
Date     : 2007-1-25
Time     : 20:28:25

Processing Rule : Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))
   Violation between Small Component C1(54.864mm,36.576mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component C2(54.864mm,48.26mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component C3(44.704mm,72.136mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component C4(149.352mm,62.484mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS1(123.952mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS2(111.252mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS3(98.552mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS4(85.852mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS5(72.644mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component DS6(59.944mm,105.664mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component P1(44.704mm,87.884mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between SOIC Component R1(142.748mm,105.156mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component R2(148.336mm,45.212mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component R3(44.704mm,54.864mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component S1(55.372mm,87.884mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component S2(55.372mm,82.804mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component S3(55.372mm,78.74mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component S4(55.372mm,74.168mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component U1(103.124mm,64.008mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component U2(130.556mm,57.404mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between DIP Component U3(74.676mm,64.008mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
   Violation between Small Component Y1(57.912mm,41.656mm) on Top Layer and 
                     Room Clock (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Clock'))   
Rule Violations :22

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
   Violation between Pad R1-2(139.473mm,106.781mm)  Top Layer and 
                     Pad R1-1(139.473mm,107.431mm)  Top Layer   
   Violation between Pad R1-3(139.473mm,106.131mm)  Top Layer and 
                     Pad R1-2(139.473mm,106.781mm)  Top Layer   
   Violation between Pad R1-4(139.473mm,105.481mm)  Top Layer and 
                     Pad R1-3(139.473mm,106.131mm)  Top Layer   
   Violation between Pad R1-5(139.473mm,104.831mm)  Top Layer and 
                     Pad R1-4(139.473mm,105.481mm)  Top Layer   
   Violation between Pad R1-6(139.473mm,104.181mm)  Top Layer and 
                     Pad R1-5(139.473mm,104.831mm)  Top Layer   
   Violation between Pad R1-7(139.473mm,103.531mm)  Top Layer and 
                     Pad R1-6(139.473mm,104.181mm)  Top Layer   
   Violation between Pad R1-8(139.473mm,102.881mm)  Top Layer and 
                     Pad R1-7(139.473mm,103.531mm)  Top Layer   
   Violation between Track (67.1576mm,40.767mm)(68.0466mm,41.656mm)  Bottom Layer and 
                     Track (67.945mm,40.894mm)(120.269mm,40.894mm)  Bottom Layer   
Rule Violations :8

Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
Rule Violations :0


Violations Detected : 30
Time Elapsed        : 00:00:00