filter.nsx

《Protel DXP 2004 SP2原理图与PCB设计（第2版）》范例源文件

filter
*SPICE Netlist generated by Advanced Sim server on 2006-12-2 1:38:11

*Schematic Netlist:
C1 0 X 50p
C2 0 OUT 50p
R1 IN X 100K
R2 X OUT 800K
R3 0 OUT 500K
V1 IN 0 DC 0 PWL(0U 5V 5U 5V 12U 0V 50U 5V 60U 5V) AC 1V 0

.SAVE 0 IN OUT X V1#branch @V1[z] @C1[i] @C2[i] @R1[i] @R2[i] @R3[i] @C1[p]
.SAVE @C2[p] @R1[p] @R2[p] @R3[p] @V1[p]

*PLOT TRAN -1 1 A=IN A=OUT A=X

*Selected Circuit Analyses:
.TRAN 2.4E-7 6E-5 0 2.4E-7

.END