analog amplifier.nsx

《Protel DXP 2004 SP2原理图与PCB设计（第2版）》范例源文件

Analog Amplifier
*SPICE Netlist generated by Advanced Sim server on 11/06/2002 5:12:15 PM

*Schematic Netlist:
RF INV OUTPUT 100k
RI INPUT INV 10k
RL OUTPUT 0 25k
XU1 0 INV VCC VEE OUTPUT UA741
V1 VCC 0 12V
V2 VEE 0 -12V
Vin INPUT 0 DC 0 SIN(0 0.1 10k 0 0) AC 1 0

.SAVE 0 INPUT INV OUTPUT VCC VEE V1#branch V2#branch Vin#branch @V1[z] @V2[z]
.SAVE @Vin[z] @RF[i] @RI[i] @RL[i] @RF[p] @RI[p] @RL[p] @V1[p] @V2[p] @Vin[p]

*PLOT AC -1 1 A=INPUT A=OUTPUT
*PLOT DC -1 1 A=INPUT A=OUTPUT
*PLOT TRAN -1 1 A=INPUT A=OUTPUT
*PLOT OP -1 1 A=INPUT A=OUTPUT

*Selected Circuit Analyses:
.DC VIN -0.7 -1.5 -0.02
.AC DEC 100 1 1E6
.TRAN 2.5E-6 0.0005 0 2.5E-6
.OP

*Models and Subcircuit:
.SUBCKT UA741 1 2 3 4 5
C1   11 12 4.664E-12
C2    6  7 20E-12
DC    5 53 DX
DE   54  5 DX
DLP  90 91 DX
DLN  92 90 DX
DP    4  3 DX
BGND 99  0 V=V(3)*.5 + V(4)*.5
BB    7 99 I=I(VB)*10.61E6 - I(VC)*10E6 + I(VE)*10E6 + I(VLP)*10E6 - I(VLN)*10E6
GA    6  0 11 12 137.7E-6
GCM   0  6 10 99 2.574E-9
IEE  10  4 DC 10.16E-6
HLIM 90  0 VLIM 1K
Q1   11  2 13 QX
Q2   12  1 14 QX
R2    6  9 100E3
RC1   3 11 7.957E3
RC2   3 12 7.957E3
RE1  13 10 2.74E3
RE2  14 10 2.74E3
REE  10 99 19.69E6
RO1   8  5 150
RO2   7 99 150
RP    3  4 18.11E3
VB    9  0 DC 0
VC    3 53 DC 2.6
VE   54  4 DC 2.6
VLIM  7  8 DC 0
VLP  91  0 DC 25
VLN   0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL QX NPN(IS=800E-18 BF=62.5)
.ENDS UA741

.END