sheet1new.nsx

《Protel DXP 2004 SP2原理图与PCB设计（第2版）》范例源文件

Sheet1new
*SPICE Netlist generated by Advanced Sim server on 2006-9-19 14:02:09

*Schematic Netlist:
C1 NetC1_1 NetC1_2 1u
C2 0 NetC1_2 102
C3 NetC3_1 VCC 33
C4 0 NetC4_2 33
C5 NetC4_2 NetC3_1 8
C6 0 VCC 102
C7 NetC3_1 NetC7_2 33
C8 NetC8_1 VCC 27
C9 NetC8_1 NetC9_2 47
L1 NetC3_1 VCC 10mH
L2 VCC NetC8_1 10mH
Q1 NetC3_1 NetC1_2 NetC4_2 NPN
Q2 NetC8_1 NetC7_2 0 NPN
R1 NetC1_2 VCC 36k
R2 0 NetC4_2 400
R3 NetC7_2 VCC 82k

.SAVE 0 NetC1_1 NetC1_2 NetC3_1 NetC4_2 NetC7_2 NetC8_1 NetC9_2 VCC @C1[i] @C2[i]
.SAVE @C3[i] @C4[i] @C5[i] @C6[i] @C7[i] @C8[i] @C9[i] @L1[i] @L2[i] @Q1[ib] @Q1[ic]
.SAVE @Q1[ie] @Q2[ib] @Q2[ic] @Q2[ie] @R1[i] @R2[i] @R3[i] @C1[p] @C2[p] @C3[p] @C4[p]
.SAVE @C5[p] @C6[p] @C7[p] @C8[p] @C9[p] @L1[p] @L2[p] @Q1[p] @Q2[p] @R1[p] @R2[p]
.SAVE @R3[p]

*PLOT TRAN -1 1 A=@C1[i] A=@C1[p] A=@C2[i] A=@C2[p] A=@C3[i] A=@C3[p] A=@C4[i]
*PLOT TRAN -1 1 A=@C4[p] A=@C5[i] A=@C5[p] A=@C6[i] A=@C6[p] A=@C7[i] A=@C7[p]
*PLOT TRAN -1 1 A=@C8[i] A=@C8[p] A=@C9[i] A=@C9[p] A=@L1[i] A=@L1[p] A=@L2[i]
*PLOT TRAN -1 1 A=@L2[p] A=NetC1_1 A=NetC1_2 A=NetC3_1 A=NetC4_2 A=NetC7_2 A=NetC8_1
*PLOT TRAN -1 1 A=NetC9_2 A=@Q1[ib] A=@Q1[ic] A=@Q1[ie] A=@Q1[p] A=@Q2[ib] A=@Q2[ic]
*PLOT TRAN -1 1 A=@Q2[ie] A=@Q2[p] A=@R1[i] A=@R1[p] A=@R2[i] A=@R2[p] A=@R3[i]
*PLOT TRAN -1 1 A=@R3[p] A=VCC
*PLOT OP -1 1 A=@C1[i] A=@C1[p] A=@C2[i] A=@C2[p] A=@C3[i] A=@C3[p] A=@C4[i]
*PLOT OP -1 1 A=@C4[p] A=@C5[i] A=@C5[p] A=@C6[i] A=@C6[p] A=@C7[i] A=@C7[p]
*PLOT OP -1 1 A=@C8[i] A=@C8[p] A=@C9[i] A=@C9[p] A=@L1[i] A=@L1[p] A=@L2[i]
*PLOT OP -1 1 A=@L2[p] A=NetC1_1 A=NetC1_2 A=NetC3_1 A=NetC4_2 A=NetC7_2 A=NetC8_1
*PLOT OP -1 1 A=NetC9_2 A=@Q1[ib] A=@Q1[ic] A=@Q1[ie] A=@Q1[p] A=@Q2[ib] A=@Q2[ic]
*PLOT OP -1 1 A=@Q2[ie] A=@Q2[p] A=@R1[i] A=@R1[p] A=@R2[i] A=@R2[p] A=@R3[i]
*PLOT OP -1 1 A=@R3[p] A=VCC

*Selected Circuit Analyses:
.TRAN 2E-8 5E-6 0 2E-8
.OP

*Models and Subcircuit:
.MODEL NPN NPN()

.END