talkthrough_tdm_c.ldf

通过BF561双核处理系统

  ** 0xFFA04000 - 0xFFA07FFF
  ** 0xFFA00000 - 0xFFA03FFF  Instr SR
  ** 0xFF908000 - 0xFF9FFFFF
  ** 0xFF904000 - 0xFF907FFF  Bank B SR/Ca
  ** 0xFF900000 - 0xFF903FFF  Bank B SR
  ** 0xFF808000 - 0xFF8FFFFF
  ** 0xFF804000 - 0xFF807FFF  Bank A SR/Ca
  ** 0xFF800000 - 0xFF803FFF  Bank A SR
  ** 0xFF701000 - 0xFF7FFFFF
  ** 0xFF700000 - 0xFF700FFF  Scratchpad
  ** 0xFF614000 - 0xFF6FFFFF
  ** 0xFF610000 - 0xFF613FFF  Instr SR/Ca
  ** 0xFF608000 - 0xFF60FFFF
  ** 0xFF604000 - 0xFF607FFF
  ** 0xFF600000 - 0xFF603FFF  Instr SR
  ** 0xFF508000 - 0xFF5FFFFF
  ** 0xFF504000 - 0xFF507FFF  Bank B SR/Ca
  ** 0xFF500000 - 0xFF503FFF  Bank B SR
  ** 0xFF408000 - 0xFF4FFFFF
  ** 0xFF404000 - 0xFF407FFF  Bank A SR/Ca
  ** 0xFF400000 - 0xFF403FFF  Bank A SR
  ** 0xFEB20000 - 0xFF3FFFFF
  ** 0xFEB00000 - 0xFEB1FFFF  L2 Shared
  ** 0xEF004000 - 0xFEAFFFFF
  ** 0xEF002000 - 0xEF003FFF
  ** 0xEF001000 - 0xEF001FFF
  ** 0xEF000800 - 0xEF000FFF
  ** 0xEF000000 - 0xEF0007FF  Boot ROM
  ** 0x30000000 - 0xEEFFFFFF
  ** 0x2C000000 - 0x2FFFFFFF  Async 3
  ** 0x28000000 - 0x2BFFFFFF  Async 2
  ** 0x24000000 - 0x27FFFFFF  Async 1
  ** 0x20000000 - 0x23FFFFFF  Async 0
  ** 0x00000000 - 0x1FFFFFFF  SDRAM MEMORY (512MB)
  */
  
   MEM_L2_SRAM             { TYPE(RAM) START(0xFEB00000) END(0xFEB1FFFF) WIDTH(8) }
   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x2C000000) END(0x2FFFFFFF) WIDTH(8) }
   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x28000000) END(0x2BFFFFFF) WIDTH(8) }
   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x24000000) END(0x27FFFFFF) WIDTH(8) }
   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x23FFFFFF) WIDTH(8) }
   /* Maximum 512MB */
   MEM_SDRAM_BANK0         { TYPE(RAM) START(0x00000004) END(0x007fffff) WIDTH(8) } 
   MEM_SDRAM_BANK1         { TYPE(RAM) START(0x00800000) END(0x00ffffff) WIDTH(8) } 
   MEM_SDRAM_BANK2         { TYPE(RAM) START(0x01000000) END(0x017fffff) WIDTH(8) } 
   MEM_SDRAM_BANK3         { TYPE(RAM) START(0x01800000) END(0x01ffffff) WIDTH(8) } 
   
   /*$VDSG<insert-new-memory-segments>                          */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-new-memory-segments>                          */
   
} /* MEMORY */

COMMON_MEMORY
{
   OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY/L2_and_L3_common_memory.sm)
   MASTERS(p0, p1)
   
   /*$VDSG<insert-user-ldf-commands-in-COMMON-MEMORY>           */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-user-ldf-commands-in-COMMON-MEMORY>           */
   
   SECTIONS
   {
      
      /*$VDSG<insert-new-sections-at-the-start-for-COMMON-MEMORY>  */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-start-for-COMMON-MEMORY>  */
      
      L2_shared_locks
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SHARED{sharing("MustShare")}(data1))
         INPUT_SECTIONS($LIBRARIES_SHARED(l2_shared))
         INPUT_SECTIONS($LIBRARIES_SHARED(primio_atomic_lock))
         INPUT_SECTIONS($LIBRARIES_SHARED(mc_data))
         INPUT_SECTIONS($LIBRARIES_SHARED(voldata))
      } > MEM_L2_SRAM

      L2_sram
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML2_CM(l2_sram))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{prefersMem("internal")}(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{prefersMem("internal")}(data1))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{!prefersMem("external")}(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{!prefersMem("external")}(data1))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(constdata))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(voldata))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(noncache_code))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(program))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(data1))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l2_sram-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l2_sram-CM>  */
         
      } > MEM_L2_SRAM

      L2_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML2_CM(L2_bsz))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{prefersMem("internal")}(bsz))
         INPUT_SECTIONS($LIBRARIES_SML2_CM{!prefersMem("external")}(bsz))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(bsz))
      } > MEM_L2_SRAM

      L2_eh_rtti
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML2_CM(ctor)  $LIBRARIES_SML3_CM(ctor))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(vtbl)  $LIBRARIES_SML3_CM(vtbl))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(.frt)  $LIBRARIES_SML3_CM(.frt))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(.edt)  $LIBRARIES_SML3_CM(.edt))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(.cht)  $LIBRARIES_SML3_CM(.cht))
         INPUT_SECTIONS($LIBRARIES_SML2_CM(.rtti) $LIBRARIES_SML3_CM(.rtti))
      } > MEM_L2_SRAM

      L2_shared
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SHARED{sharing("MustShare")}(data1))
         INPUT_SECTIONS($LIBRARIES_SHARED(l2_shared))
         INPUT_SECTIONS($LIBRARIES_SHARED(primio_atomic_lock))
         INPUT_SECTIONS($LIBRARIES_SHARED(mc_data))
      } > MEM_L2_SRAM

      sdram_bank0
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank0-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank0-CM>  */
         
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_data_bank0))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_bank0))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(data1))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(voldata))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(constdata))
      } > MEM_SDRAM_BANK0

      sdram_bank0_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_bsz))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(bsz))
      } > MEM_SDRAM_BANK0

      sdram_bank2
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram0))
         
         /*$VDSG<insert-input-sections-in-the-middle-of-sdram_bank2-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-in-the-middle-of-sdram_bank2-CM>  */
         
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_data_bank2))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_bank2))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(program))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2-CM>  */
         
      } > MEM_SDRAM_BANK2

      sdram_bank3
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank3-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank3-CM>  */
         
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_data_bank3))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_bank3))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(data1))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(voldata))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3-CM>  */
         
      } > MEM_SDRAM_BANK3

      sdram_bank1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram0))
         
         /*$VDSG<insert-input-sections-in-the-middle-of-sdram_bank1-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-in-the-middle-of-sdram_bank1-CM>  */
         
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_data_bank1))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(sdram_bank1))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(program))
         INPUT_SECTIONS($LIBRARIES_SML3_CM(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1-CM>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1-CM>  */
         
      } > MEM_SDRAM_BANK1

      
      /*$VDSG<insert-new-sections-at-the-end-for-COMMON-MEMORY>  */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-end-for-COMMON-MEMORY>  */
      
   } /* SECTIONS */
} /* COMMON_MEMORY */

PROCESSOR p0
{
   
   MEMORY
   {
      MEM_A_L1_SCRATCH        { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
      MEM_A_L1_CODE           { TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) }
      MEM_A_L1_DATA_B         { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }
      MEM_A_L1_DATA_A         { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }
      
      /*$VDSG<insert-new-memory-segments-for-CORE-A>            */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-memory-segments-for-CORE-A>            */
      
   } /* MEMORY */
   
   OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY/p0.dxe)
   RESOLVE(start, 0xFFA00000)
   KEEP(start,_main)
   
   /*$VDSG<insert-user-ldf-commands-for-CORE-A>                 */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-user-ldf-commands-for-CORE-A>                 */
   
   SECTIONS
   {
      /* FEB1FC00->FEB1FFFF : Reserved in boot Phase for 2nd stage boot loader. */
      RESERVE(___ssld=0xFEB1FC00, ___lssld = 0x400)
      
      /*$VDSG<insert-new-sections-at-the-start-for-CORE-A>      */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-start-for-CORE-A>      */
      
      scratchpad
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-A>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-A>  */
         
      } > MEM_A_L1_SCRATCH

      L1_code
      {
         INPUT_SECTION_ALIGN(4)
         __CORE = 0;
         INPUT_SECTIONS($OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(program))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         
      } > MEM_A_L1_CODE