mulf2m.vhd
来自「椭圆曲线加密算法中的乘法器的生成」· VHDL 代码 · 共 72 行
VHD
72 行
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mulf2m is
generic(size:integer:=4);
port(
clk,rst,en:in std_logic;
a,b:in std_logic_vector(size downto 0);
fx:in std_logic_vector(size downto 0);
done:buffer std_logic;
c:buffer std_logic_vector(size downto 0));
end mulf2m;
architecture pipomul of mulf2m is
type multistate is(idle,working);
signal state:multistate;
signal buff_a:std_logic_vector(size downto 0);
signal buff_b:std_logic_vector(size downto 0);
signal srlcount:integer range 0 to size;
signal carry_bit:std_logic;
signal present_a:std_logic;
begin
reg_shift:process(rst,clk)
begin
if rst='1' then
state<=idle;
done<='0';
c<=(others=>'0');
elsif(clk'event and clk='1')then
case state is
when idle=>
if en='1' then
srlcount<=0;
buff_a<=a;
present_a<=a(0);
buff_b<=b;
carry_bit<=b(size-1);
done<='0';
c<=(others=>'0');
state<=working;
end if;
when working=>
if carry_bit='0' then
for i in size-2 downto 0 loop
buff_b(i+1)<=buff_b(i);
end loop;
buff_b(0)<='0';
else
for i in size-2 downto 0 loop
buff_b(i+1)<=buff_b(i) xor fx(i+1);
end loop;
buff_b(0)<=fx(0);
end if;
carry_bit<=buff_b(size-2);
present_a<=buff_a(1);
for j in 0 to size-2 loop
buff_a(j)<=buff_a(j+1);
end loop;
buff_a(size-1)<='0';
srlcount<=srlcount+1;
if present_a='1' then
c<=c xor buff_b;
end if;
if srlcount=size-1 then
done<='1';
state<=idle;
end if;
when others=>
state<=idle;
end case;
end if;
end process;
end pipomul;
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