mux12.v
来自「嵌入式risc处理器源码」· Verilog 代码 · 共 50 行
V
50 行
/****************************************************************************************
MODULE: Sub Level Multiplexer Block
FILE NAME: mux12.v
VERSION: 1.0
DATE: September 28th, 2001
AUTHOR: Hossein Amidi
COMPANY: California Unique Electrical Co.
CODE TYPE: Register Transfer Level
Instantiations:
DESCRIPTION:
Sub Level RTL Multiplexer block
Hossein Amidi
(C) September 2001
California Unique Electric
***************************************************************************************/
`timescale 1ns / 1ps
module MUX12 ( // Input
A_in,
B_in,
A_Select,
// Output
Out
);
// Parameter
parameter AddrWidth = 24;
// Input
input [AddrWidth - 1 : 0] A_in;
input [AddrWidth - 1 : 0] B_in;
input A_Select;
// Output
output [AddrWidth - 1 : 0] Out;
//Dataflow description of MUX12
assign Out = A_Select ? A_in : B_in;
endmodule
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?