iom128.h

AVR megal128下的ucos_ii

#define    ISC61        5
#define    ISC60        4
#define    ISC51        3
#define    ISC50        2
#define    ISC41        1
#define    ISC40        0

/* External Interrupt MaSK register */
#define    INT7         7
#define    INT6         6   
#define    INT5         5
#define    INT4         4
#define    INT3         3
#define    INT2         2
#define    INT1         1
#define    INT0         0

/* 葂ternal Interrupt Flag Register */
#define    INTF7        7
#define    INTF6        6
#define    INTF5        5
#define    INTF4        4
#define INTF3   3
#define INTF    2
#define INTF2   2
#define INTF1   1
#define INTF0   0

/* TIMSK Timer/Counter Interrupt MaSK register */ 
#define    OCIE2        7
#define    TOIE2        6
#define    TICIE1       5
#define    OCIE1A       4
#define    OCIE1B       3
#define    TOIE1        2
#define    OCIE0        1
#define    TOIE0        0

/* Timer/Counter Interrupt Flag Register */
#define    OCF2         7
#define    TOV2         6
#define    ICF1         5
#define    OCF1A        4
#define    OCF1B        3
#define    TOV1         2
#define    OCF0         1
#define    TOV0         0      

/* MCU general Control Register */
#define    SRE          7
#define    SRW10        6
#define    SE           5
#define    SM1          4
#define    SM0          3
#define SM2     2
#define IVSEL   1
#define IVCE    0

/* MCUCSR MCU Control and Status Register */    
#define JTD 7
#define JTRF    4
#define WDRF    3
#define BORF    2
#define    EXTRF       1
#define    PORF        0

/* TCCR0 Timer/Counter 0 Control Register */
#define FOC0    7
#define WGM00   6
#define COM01   5
#define COM00   4
#define WGM01   3
#define    CS02         2
#define    CS01         1
#define    CS00         0

/* ASSR */
#define AS0     3
#define TCN0UB  2
#define OCR0UB  1
#define TCR0UB  0

/* Timer/Counter 0 Control Register */
#define    PWM0         6
#define    COM01        5
#define    COM00        4
#define    CTC0         3
#define    CS02         2
#define    CS01         1
#define    CS00         0

/* Timer/Counter 0 Asynchronous Control & Status Register */ 
#define    AS0          3
#define    TCN0UB       2
#define    OCR0UB       1
#define    TCR0UB       0 

/* TCCR1A Timer/Counter 1 Control Register */ 
#define    COM1A1       7
#define    COM1A0       6
#define    COM1B1       5
#define    COM1B0       4
#define    COM1C1       3
#define COM1C0          2
#define WGM11           1
#define    WGM10        0

/* TCCR1B Timer/Counter 1 Control and Status Register */
#define    ICNC1        7
#define    ICES1        6
#define WGM13   4
#define WGM12   3
#define    CS12         2
#define    CS11         1
#define    CS10         0

/* TCCR2 Timer/Counter 2 Control register */ 
#define FOC2        7
#define    WGM20    6 
#define    COM21        5
#define    COM20        4
#define    WGM21        3
#define    CS22         2
#define    CS21         1
#define    CS20         0

#define IDRD	7
#define OCDR7	7
#define OCDR6	6
#define OCDR5	5
#define OCDR4	4
#define OCDR3	3
#define OCDR2	2
#define OCDR1	1
#define OCDR0	0

/* Watchdog Timer Control Register */ 
#define    WDCE         4
#define    WDE          3
#define    WDP2         2
#define    WDP1         1
#define    WDP0         0

/* SFIOR */
#define TSM     7
#define ADHSM   4
#define ACME    3
#define PUD     2
#define PSR0    1
#define PSR321  0

/* EEPROM Control Register */
#define    EERIE        3
#define    EEMWE        2
#define    EEWE         1
#define    EERE         0

/* Data Register, Port A */
#define    PORTA7          7
#define    PORTA6          6
#define    PORTA5          5
#define    PORTA4          4
#define    PORTA3          3
#define    PORTA2          2
#define    PORTA1          1
#define    PORTA0          0

/* Data Direction Register, Port A */ 
#define    DDA7         7
#define    DDA6         6
#define    DDA5         5
#define    DDA4         4
#define    DDA3         3
#define    DDA2         2
#define    DDA1         1
#define    DDA0         0

/* Input Pins, Port A */ 
#define    PINA7        7
#define    PINA6        6
#define    PINA5        5
#define    PINA4        4
#define    PINA3        3
#define    PINA2        2
#define    PINA1        1
#define    PINA0        0

/* Data Register, Port B */ 
#define    PORTB7          7
#define    PORTB6          6
#define    PORTB5          5
#define    PORTB4          4
#define    PORTB3          3
#define    PORTB2          2
#define    PORTB1          1
#define    PORTB0          0

/* Data Direction Register, Port B */
#define    DDB7         7
#define    DDB6         6
#define    DDB5         5
#define    DDB4         4
#define    DDB3         3
#define    DDB2         2
#define    DDB1         1
#define    DDB0         0

/* Input Pins, Port B */
#define    PINB7        7
#define    PINB6        6
#define    PINB5        5
#define    PINB4        4
#define    PINB3        3
#define    PINB2        2
#define    PINB1        1
#define    PINB0        0

/* Data Register, Port C */
#define    PORTC7          7
#define    PORTC6          6
#define    PORTC5          5
#define    PORTC4          4
#define    PORTC3          3
#define    PORTC2          2
#define    PORTC1          1
#define    PORTC0          0

/* Data Direction Register, Port C */
#define    DDC7         7
#define    DDC6         6
#define    DDC5         5
#define    DDC4         4
#define    DDC3         3
#define    DDC2         2
#define    DDC1         1
#define    DDC0         0

/* Input Pins, Port C */
#define    PINC7        7
#define    PINC6        6
#define    PINC5        5
#define    PINC4        4
#define    PINC3        3
#define    PINC2        2
#define    PINC1        1
#define    PINC0        0

/* Data Register, Port D */
#define    PORTD7          7
#define    PORTD6          6
#define    PORTD5          5
#define    PORTD4          4
#define    PORTD3          3
#define    PORTD2          2
#define    PORTD1          1
#define    PORTD0          0

/* Data Direction Register, Port D */
#define    DDD7         7
#define    DDD6         6
#define    DDD5         5
#define    DDD4         4
#define    DDD3         3
#define    DDD2         2
#define    DDD1         1
#define    DDD0         0

/* Input Pins, Port D */
#define    PIND7        7
#define    PIND6        6
#define    PIND5        5
#define    PIND4        4
#define    PIND3        3
#define    PIND2        2
#define    PIND1        1
#define    PIND0        0

/* Data Register, Port E */
#define    PE7          7
#define    PE6          6
#define    PE5          5
#define    PE4          4
#define    PE3          3
#define    PE2          2
#define    PE1          1
#define    PE0          0

/* Data Direction Register, Port E */
#define    DDE7         7
#define    DDE6         6
#define    DDE5         5
#define    DDE4         4
#define    DDE3         3
#define    DDE2         2
#define    DDE1         1
#define    DDE0         0

/* Input Pins, Port E */
#define    PINE7        7
#define    PINE6        6
#define    PINE5        5
#define    PINE4        4
#define    PINE3        3
#define    PINE2        2
#define    PINE1        1
#define    PINE0        0

/* Input Pins, Port F */
#define    PINF7        7
#define    PINF6        6
#define    PINF5        5
#define    PINF4        4
#define    PINF3        3
#define    PINF2        2
#define    PINF1        1
#define    PINF0        0

/* SPI Status Register */ 
#define    SPIF         7
#define    WCOL         6
#define SPI2X	0

/* SPI Control Register */
#define    SPIE         7
#define    SPE          6
#define    DORD         5
#define    MSTR         4
#define    CPOL         3
#define    CPHA         2
#define    SPR1         1
#define    SPR0         0

/* UCSR0A */
#define    RXC0          7
#define    TXC0          6
#define    UDRE0         5
#define    FE0           4
#define    DOR0          3
#define UPE0     2
#define U2X0    1
#define MPCM0   0

/* UCSR0B */
#define    RXCIE0        7
#define    TXCIE0        6
#define    UDRIE0        5
#define    RXEN0         4
#define    TXEN0         3
#define    UCSZ02        2
#define    RXB80         1
#define    TXB80         0

/* UCSR1A */
#define    RXC1          7
#define    TXC1          6
#define    UDRE1         5
#define    FE1           4
#define    DOR1          3
#define UPE1     2
#define U2X1    1
#define MPCM1   0

/* UCSR1B */
#define    RXCIE1        7
#define    TXCIE1        6
#define    UDRIE1        5
#define    RXEN1         4
#define    TXEN1         3
#define    UCSZ12        2
#define    RXB81         1
#define    TXB81         0

/* Analog Comparator Control and Status Register */
#define    ACD          7
#define ACBG            6
#define    ACO          5
#define    ACI          4
#define    ACIE         3
#define    ACIC         2
#define    ACIS1        1
#define    ACIS0        0

/* ADC Control and status register */
#define    ADEN         7
#define    ADSC         6
#define    ADRF         5
#define    ADIF         4
#define    ADIE         3
#define    ADPS2        2
#define    ADPS1        1
#define    ADPS0        0

/* ADMUX ADC Multiplexer select */
#define REFS1       7
#define REFS0       6
#define ADLAR       5
#define    MUX4         4
#define    MUX3         3
#define    MUX2         2
#define    MUX1         1
#define    MUX0         0

/* Interrupt Vectors */
#define IT_RESET        1
#define IT_INT0         2
#define IT_INT1         3
#define IT_INT2         4
#define IT_INT3         5
#define IT_INT4         6
#define IT_INT5         7
#define IT_INT6         8
#define IT_INT7         9
#define IT_TIMER2_COMP  10
#define IT_TIMER2_OVF   11
#define IT_TIMER1_CAPT  12
#define IT_TIMER1_COMPA 13
#define IT_TIMER1_COMPB 14
#define IT_TIMER1_OVF   15
#define IT_TIMER0_COMP  16
#define IT_TIMER0_OVF   17
#define IT_SPI_STC      18
#define IT_USART0_RX    19
#define IT_USART0_UDRE  20
#define IT_USART0_TX    21
#define IT_ADC          22
#define IT_EE_READY     23
#define IT_ANALOG_COMP  24
#define IT_TIMER1_COMPC 25
#define IT_TIMER3_CAPT  26
#define IT_TIMER3_COMPA 27
#define IT_TIMER3_COMPB 28
#define IT_TIMER3_COMPC 29
#define IT_TIMER3_OVF   30
#define IT_USART1_RX    31
#define IT_USART1_UDRE  32
#define IT_USART1_TX    33
#define IT_TWI          34
#define IT_SPM_READY    35

#endif