xulieqi.tan.rpt

实现LED灯的点亮

; N/A           ; None        ; -4.873 ns ; DIN8[2] ; SCHK:U2|Q[3] ; CLK      ;
; N/A           ; None        ; -4.883 ns ; DIN8[6] ; SCHK:U2|Q[0] ; CLK      ;
; N/A           ; None        ; -4.884 ns ; DIN8[6] ; SCHK:U2|Q[3] ; CLK      ;
; N/A           ; None        ; -5.006 ns ; DIN8[5] ; SCHK:U2|Q[0] ; CLK      ;
; N/A           ; None        ; -5.007 ns ; DIN8[5] ; SCHK:U2|Q[3] ; CLK      ;
; N/A           ; None        ; -5.069 ns ; DIN8[0] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.113 ns ; DIN8[4] ; SCHK:U2|Q[0] ; CLK      ;
; N/A           ; None        ; -5.114 ns ; DIN8[4] ; SCHK:U2|Q[3] ; CLK      ;
; N/A           ; None        ; -5.118 ns ; DIN8[2] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.129 ns ; DIN8[6] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.225 ns ; DIN8[0] ; SCHK:U2|Q[1] ; CLK      ;
; N/A           ; None        ; -5.252 ns ; DIN8[5] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.274 ns ; DIN8[2] ; SCHK:U2|Q[1] ; CLK      ;
; N/A           ; None        ; -5.285 ns ; DIN8[6] ; SCHK:U2|Q[1] ; CLK      ;
; N/A           ; None        ; -5.359 ns ; DIN8[4] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.408 ns ; DIN8[5] ; SCHK:U2|Q[1] ; CLK      ;
; N/A           ; None        ; -5.438 ns ; DIN8[3] ; SCHK:U2|Q[0] ; CLK      ;
; N/A           ; None        ; -5.439 ns ; DIN8[3] ; SCHK:U2|Q[3] ; CLK      ;
; N/A           ; None        ; -5.515 ns ; DIN8[4] ; SCHK:U2|Q[1] ; CLK      ;
; N/A           ; None        ; -5.684 ns ; DIN8[3] ; SCHK:U2|Q[2] ; CLK      ;
; N/A           ; None        ; -5.840 ns ; DIN8[3] ; SCHK:U2|Q[1] ; CLK      ;
+---------------+-------------+-----------+---------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Jul 09 21:54:34 2002
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off xulieqi -c xulieqi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 420.17 MHz between source register "XULIE:U1|current_state.s5" and destination register "SCHK:U2|Q[1]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.105 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y17_N29; Fanout = 2; REG Node = 'XULIE:U1|current_state.s5'
            Info: 2: + IC(0.329 ns) + CELL(0.150 ns) = 0.479 ns; Loc. = LCCOMB_X32_Y17_N16; Fanout = 1; COMB Node = 'XULIE:U1|Selector0~73'
            Info: 3: + IC(0.277 ns) + CELL(0.438 ns) = 1.194 ns; Loc. = LCCOMB_X32_Y17_N30; Fanout = 5; COMB Node = 'XULIE:U1|Selector0~75'
            Info: 4: + IC(0.277 ns) + CELL(0.150 ns) = 1.621 ns; Loc. = LCCOMB_X32_Y17_N2; Fanout = 1; COMB Node = 'SCHK:U2|Mux2~101'
            Info: 5: + IC(0.250 ns) + CELL(0.150 ns) = 2.021 ns; Loc. = LCCOMB_X32_Y17_N20; Fanout = 1; COMB Node = 'SCHK:U2|Mux2~102'
            Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.105 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
            Info: Total cell delay = 0.972 ns ( 46.18 % )
            Info: Total interconnect delay = 1.133 ns ( 53.82 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.696 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.042 ns) + CELL(0.537 ns) = 2.696 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
                Info: Total cell delay = 1.536 ns ( 56.97 % )
                Info: Total interconnect delay = 1.160 ns ( 43.03 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.696 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.042 ns) + CELL(0.537 ns) = 2.696 ns; Loc. = LCFF_X32_Y17_N29; Fanout = 2; REG Node = 'XULIE:U1|current_state.s5'
                Info: Total cell delay = 1.536 ns ( 56.97 % )
                Info: Total interconnect delay = 1.160 ns ( 43.03 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "SCHK:U2|Q[1]" (data pin = "DIN8[3]", clock pin = "CLK") is 6.070 ns
    Info: + Longest pin to register delay is 8.802 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B14; Fanout = 1; PIN Node = 'DIN8[3]'
        Info: 2: + IC(5.889 ns) + CELL(0.437 ns) = 7.176 ns; Loc. = LCCOMB_X32_Y17_N16; Fanout = 1; COMB Node = 'XULIE:U1|Selector0~73'
        Info: 3: + IC(0.277 ns) + CELL(0.438 ns) = 7.891 ns; Loc. = LCCOMB_X32_Y17_N30; Fanout = 5; COMB Node = 'XULIE:U1|Selector0~75'
        Info: 4: + IC(0.277 ns) + CELL(0.150 ns) = 8.318 ns; Loc. = LCCOMB_X32_Y17_N2; Fanout = 1; COMB Node = 'SCHK:U2|Mux2~101'
        Info: 5: + IC(0.250 ns) + CELL(0.150 ns) = 8.718 ns; Loc. = LCCOMB_X32_Y17_N20; Fanout = 1; COMB Node = 'SCHK:U2|Mux2~102'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 8.802 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
        Info: Total cell delay = 2.109 ns ( 23.96 % )
        Info: Total interconnect delay = 6.693 ns ( 76.04 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.696 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.042 ns) + CELL(0.537 ns) = 2.696 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
        Info: Total cell delay = 1.536 ns ( 56.97 % )
        Info: Total interconnect delay = 1.160 ns ( 43.03 % )
Info: tco from clock "CLK" to destination pin "LED7S[0]" through register "SCHK:U2|Q[1]" is 9.254 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.696 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.042 ns) + CELL(0.537 ns) = 2.696 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
        Info: Total cell delay = 1.536 ns ( 56.97 % )
        Info: Total interconnect delay = 1.160 ns ( 43.03 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 6.308 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y17_N21; Fanout = 4; REG Node = 'SCHK:U2|Q[1]'
        Info: 2: + IC(0.781 ns) + CELL(0.398 ns) = 1.179 ns; Loc. = LCCOMB_X32_Y17_N12; Fanout = 3; COMB Node = 'SCHK:U2|Equal0~34'
        Info: 3: + IC(2.341 ns) + CELL(2.788 ns) = 6.308 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'LED7S[0]'
        Info: Total cell delay = 3.186 ns ( 50.51 % )
        Info: Total interconnect delay = 3.122 ns ( 49.49 % )
Info: th for register "SCHK:U2|Q[0]" (data pin = "DIN8[1]", clock pin = "CLK") is -0.589 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.696 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.042 ns) + CELL(0.537 ns) = 2.696 ns; Loc. = LCFF_X32_Y17_N15; Fanout = 5; REG Node = 'SCHK:U2|Q[0]'
        Info: Total cell delay = 1.536 ns ( 56.97 % )
        Info: Total interconnect delay = 1.160 ns ( 43.03 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.551 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 1; PIN Node = 'DIN8[1]'
        Info: 2: + IC(1.141 ns) + CELL(0.420 ns) = 2.540 ns; Loc. = LCCOMB_X32_Y17_N8; Fanout = 1; COMB Node = 'XULIE:U1|Selector0~71'
        Info: 3: + IC(0.260 ns) + CELL(0.242 ns) = 3.042 ns; Loc. = LCCOMB_X32_Y17_N30; Fanout = 5; COMB Node = 'XULIE:U1|Selector0~75'
        Info: 4: + IC(0.275 ns) + CELL(0.150 ns) = 3.467 ns; Loc. = LCCOMB_X32_Y17_N14; Fanout = 1; COMB Node = 'SCHK:U2|Mux2~100'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 3.551 ns; Loc. = LCFF_X32_Y17_N15; Fanout = 5; REG Node = 'SCHK:U2|Q[0]'
        Info: Total cell delay = 1.875 ns ( 52.80 % )
        Info: Total interconnect delay = 1.676 ns ( 47.20 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 121 megabytes of memory during processing
    Info: Processing ended: Tue Jul 09 21:54:36 2002
    Info: Elapsed time: 00:00:02