📄 decl7s.vhd
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Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity DECL7S is
port(AB: in std_logic_vector(3 downto 0);
LED7S: out std_logic_vector(6 downto 0) );
end;
architecture behav of DECL7S is
begin
process(AB)
begin
case AB is
when "1010"=>LED7S<="0001000";
when "1011"=>LED7S<="0000011" ;
when OTHERS=>NULL;
end case;
end process;
end behav;
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