rf.c

VIA VT6656 USB linux source code.

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File: rf.c
 *
 * Purpose: rf function code
 *
 * Author: Jerry Chen
 *
 * Date: Feb. 19, 2004
 *
 * Functions:
 *      IFRFbWriteEmbeded      - Embeded write RF register via MAC
 *
 * Revision History:
 *
 */

#if !defined(__MAC_H__)
#include "mac.h"
#endif
#if !defined(__RF_H__)
#include "rf.h"
#endif
#if !defined(__BASEBAND_H__)
#include "baseband.h"
#endif
#if !defined(__CONTROL_H__)
#include "control.h"
#endif
#if !defined(__RNDIS_H__)
#include "rndis.h"
#endif
#if !defined(__DATARATE_H__)
#include "datarate.h"
#endif                      

static int          msglevel                =MSG_LEVEL_INFO;
//static int          msglevel                =MSG_LEVEL_DEBUG;
/*---------------------  Static Definitions -------------------------*/
#define BY_AL2230_REG_LEN     23 //24bit
#define CB_AL2230_INIT_SEQ    15
#define AL2230_PWR_IDX_LEN    64

#define BY_AL7230_REG_LEN     23 //24bit
#define CB_AL7230_INIT_SEQ    16
#define AL7230_PWR_IDX_LEN    64

//{{RobertYu:20051111
#define BY_VT3226_REG_LEN     23
#define CB_VT3226_INIT_SEQ    11
#define VT3226_PWR_IDX_LEN    64
//}}

//{{RobertYu:20060609
#define BY_VT3342_REG_LEN     23
#define CB_VT3342_INIT_SEQ    13
#define VT3342_PWR_IDX_LEN    64
//}}

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/




BYTE abyAL2230InitTable[CB_AL2230_INIT_SEQ][3] = {
    {0x03, 0xF7, 0x90},
    {0x03, 0x33, 0x31},
    {0x01, 0xB8, 0x02},
    {0x00, 0xFF, 0xF3},
    {0x00, 0x05, 0xA4},
    {0x0F, 0x4D, 0xC5},   //RobertYu:20060814    
    {0x08, 0x05, 0xB6},
    {0x01, 0x47, 0xC7},
    {0x00, 0x06, 0x88},
    {0x04, 0x03, 0xB9},
    {0x00, 0xDB, 0xBA},
    {0x00, 0x09, 0x9B},
    {0x0B, 0xDF, 0xFC},
    {0x00, 0x00, 0x0D},
    {0x00, 0x58, 0x0F}
    };

BYTE abyAL2230ChannelTable0[CB_MAX_CHANNEL_24G][3] = {
    {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz
    {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz
    {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz
    {0x03, 0xE7, 0x90}, // channel = 4, Tf = 2427MHz
    {0x03, 0xF7, 0xA0}, // channel = 5, Tf = 2432MHz
    {0x03, 0xF7, 0xA0}, // channel = 6, Tf = 2437MHz
    {0x03, 0xE7, 0xA0}, // channel = 7, Tf = 2442MHz
    {0x03, 0xE7, 0xA0}, // channel = 8, Tf = 2447MHz
    {0x03, 0xF7, 0xB0}, // channel = 9, Tf = 2452MHz
    {0x03, 0xF7, 0xB0}, // channel = 10, Tf = 2457MHz
    {0x03, 0xE7, 0xB0}, // channel = 11, Tf = 2462MHz
    {0x03, 0xE7, 0xB0}, // channel = 12, Tf = 2467MHz
    {0x03, 0xF7, 0xC0}, // channel = 13, Tf = 2472MHz
    {0x03, 0xE7, 0xC0}  // channel = 14, Tf = 2412M
    };

BYTE abyAL2230ChannelTable1[CB_MAX_CHANNEL_24G][3] = {
    {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
    {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
    {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
    {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
    {0x03, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
    {0x0B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
    {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
    {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
    {0x03, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
    {0x0B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
    {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
    {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
    {0x03, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
    {0x06, 0x66, 0x61}  // channel = 14, Tf = 2412M
    };
        
// 40MHz reference frequency 
// Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
BYTE abyAL7230InitTable[CB_AL7230_INIT_SEQ][3] = {
    {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a
    {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a
    {0x84, 0x1F, 0xF2}, // Need modify for 11a: 451FE2
    {0x3F, 0xDF, 0xA3}, // Need modify for 11a: 5FDFA3
    {0x7F, 0xD7, 0x84}, // 11b/g    // Need modify for 11a
    //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
    // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
    {0x80, 0x2B, 0x55}, // Need modify for 11a: 8D1B55
    {0x56, 0xAF, 0x36}, 
    {0xCE, 0x02, 0x07}, // Need modify for 11a: 860207
    {0x6E, 0xBC, 0x98}, 
    {0x22, 0x1B, 0xB9}, 
    {0xE0, 0x00, 0x0A}, // Need modify for 11a: E0600A
    {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
    //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
    // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
    {0x00, 0x0A, 0x3C}, // Need modify for 11a: 00143C
    {0xFF, 0xFF, 0xFD},
    {0x00, 0x00, 0x0E},
    {0x1A, 0xBA, 0x8F} // Need modify for 11a: 12BACF
    };

BYTE abyAL7230InitTableAMode[CB_AL7230_INIT_SEQ][3] = {
    {0x2F, 0xF5, 0x20}, // Channel184 // Need modify for 11b/g
    {0x00, 0x00, 0x01}, // Channel184 // Need modify for 11b/g
    {0x45, 0x1F, 0xE2}, // Need modify for 11b/g
    {0x5F, 0xDF, 0xA3}, // Need modify for 11b/g
    {0x6F, 0xD7, 0x84}, // 11a    // Need modify for 11b/g
    {0x85, 0x3F, 0x55}, // Need modify for 11b/g, RoberYu:20050113
    {0x56, 0xAF, 0x36}, 
    {0xCE, 0x02, 0x07}, // Need modify for 11b/g
    {0x6E, 0xBC, 0x98}, 
    {0x22, 0x1B, 0xB9}, 
    {0xE0, 0x60, 0x0A}, // Need modify for 11b/g
    {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
    {0x00, 0x14, 0x7C}, // Need modify for 11b/g
    {0xFF, 0xFF, 0xFD},
    {0x00, 0x00, 0x0E},
    {0x12, 0xBA, 0xCF} // Need modify for 11b/g
    };

BYTE abyAL7230ChannelTable0[CB_MAX_CHANNEL][3] = {
    {0x20, 0x37, 0x90}, // channel =  1, Tf = 2412MHz
    {0x20, 0x37, 0x90}, // channel =  2, Tf = 2417MHz
    {0x20, 0x37, 0x90}, // channel =  3, Tf = 2422MHz
    {0x20, 0x37, 0x90}, // channel =  4, Tf = 2427MHz
    {0x20, 0x37, 0xA0}, // channel =  5, Tf = 2432MHz
    {0x20, 0x37, 0xA0}, // channel =  6, Tf = 2437MHz
    {0x20, 0x37, 0xA0}, // channel =  7, Tf = 2442MHz
    {0x20, 0x37, 0xA0}, // channel =  8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xB0}, // channel =  9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xB0}, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xB0}, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xB0}, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xC0}, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
    {0x20, 0x37, 0xC0}, // channel = 14, Tf = 2484MHz

    // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    {0x0F, 0xF5, 0x20}, // channel = 183, Tf = 4915MHz (15)
    {0x2F, 0xF5, 0x20}, // channel = 184, Tf = 4920MHz (16)
    {0x0F, 0xF5, 0x20}, // channel = 185, Tf = 4925MHz (17)
    {0x0F, 0xF5, 0x20}, // channel = 187, Tf = 4935MHz (18)
    {0x2F, 0xF5, 0x20}, // channel = 188, Tf = 4940MHz (19)
    {0x0F, 0xF5, 0x20}, // channel = 189, Tf = 4945MHz (20)
    {0x2F, 0xF5, 0x30}, // channel = 192, Tf = 4960MHz (21)
    {0x2F, 0xF5, 0x30}, // channel = 196, Tf = 4980MHz (22)

    // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 
    // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)

    {0x0F, 0xF5, 0x40}, // channel =   7, Tf = 5035MHz (23)
    {0x2F, 0xF5, 0x40}, // channel =   8, Tf = 5040MHz (24)
    {0x0F, 0xF5, 0x40}, // channel =   9, Tf = 5045MHz (25)
    {0x0F, 0xF5, 0x40}, // channel =  11, Tf = 5055MHz (26)
    {0x2F, 0xF5, 0x40}, // channel =  12, Tf = 5060MHz (27)
    {0x2F, 0xF5, 0x50}, // channel =  16, Tf = 5080MHz (28)
    {0x2F, 0xF5, 0x60}, // channel =  34, Tf = 5170MHz (29)
    {0x2F, 0xF5, 0x60}, // channel =  36, Tf = 5180MHz (30)
    {0x2F, 0xF5, 0x70}, // channel =  38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
    {0x2F, 0xF5, 0x70}, // channel =  40, Tf = 5200MHz (32)
    {0x2F, 0xF5, 0x70}, // channel =  42, Tf = 5210MHz (33)
    {0x2F, 0xF5, 0x70}, // channel =  44, Tf = 5220MHz (34)
    {0x2F, 0xF5, 0x70}, // channel =  46, Tf = 5230MHz (35)
    {0x2F, 0xF5, 0x70}, // channel =  48, Tf = 5240MHz (36)
    {0x2F, 0xF5, 0x80}, // channel =  52, Tf = 5260MHz (37)
    {0x2F, 0xF5, 0x80}, // channel =  56, Tf = 5280MHz (38)
    {0x2F, 0xF5, 0x80}, // channel =  60, Tf = 5300MHz (39)
    {0x2F, 0xF5, 0x90}, // channel =  64, Tf = 5320MHz (40)

    {0x2F, 0xF5, 0xC0}, // channel = 100, Tf = 5500MHz (41)
    {0x2F, 0xF5, 0xC0}, // channel = 104, Tf = 5520MHz (42)
    {0x2F, 0xF5, 0xC0}, // channel = 108, Tf = 5540MHz (43)
    {0x2F, 0xF5, 0xD0}, // channel = 112, Tf = 5560MHz (44)
    {0x2F, 0xF5, 0xD0}, // channel = 116, Tf = 5580MHz (45)
    {0x2F, 0xF5, 0xD0}, // channel = 120, Tf = 5600MHz (46)
    {0x2F, 0xF5, 0xE0}, // channel = 124, Tf = 5620MHz (47)
    {0x2F, 0xF5, 0xE0}, // channel = 128, Tf = 5640MHz (48)
    {0x2F, 0xF5, 0xE0}, // channel = 132, Tf = 5660MHz (49)
    {0x2F, 0xF5, 0xF0}, // channel = 136, Tf = 5680MHz (50)
    {0x2F, 0xF5, 0xF0}, // channel = 140, Tf = 5700MHz (51)
    {0x2F, 0xF6, 0x00}, // channel = 149, Tf = 5745MHz (52)
    {0x2F, 0xF6, 0x00}, // channel = 153, Tf = 5765MHz (53)
    {0x2F, 0xF6, 0x00}, // channel = 157, Tf = 5785MHz (54)
    {0x2F, 0xF6, 0x10}, // channel = 161, Tf = 5805MHz (55)
    {0x2F, 0xF6, 0x10} // channel = 165, Tf = 5825MHz (56)
    };

BYTE abyAL7230ChannelTable1[CB_MAX_CHANNEL][3] = {
    {0x13, 0x33, 0x31}, // channel =  1, Tf = 2412MHz
    {0x1B, 0x33, 0x31}, // channel =  2, Tf = 2417MHz
    {0x03, 0x33, 0x31}, // channel =  3, Tf = 2422MHz
    {0x0B, 0x33, 0x31}, // channel =  4, Tf = 2427MHz
    {0x13, 0x33, 0x31}, // channel =  5, Tf = 2432MHz
    {0x1B, 0x33, 0x31}, // channel =  6, Tf = 2437MHz
    {0x03, 0x33, 0x31}, // channel =  7, Tf = 2442MHz
    {0x0B, 0x33, 0x31}, // channel =  8, Tf = 2447MHz
    {0x13, 0x33, 0x31}, // channel =  9, Tf = 2452MHz
    {0x1B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
    {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
    {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
    {0x13, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
    {0x06, 0x66, 0x61}, // channel = 14, Tf = 2484MHz

    // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)    
    {0x1D, 0x55, 0x51}, // channel = 183, Tf = 4915MHz (15)
    {0x00, 0x00, 0x01}, // channel = 184, Tf = 4920MHz (16)
    {0x02, 0xAA, 0xA1}, // channel = 185, Tf = 4925MHz (17)
    {0x08, 0x00, 0x01}, // channel = 187, Tf = 4935MHz (18)
    {0x0A, 0xAA, 0xA1}, // channel = 188, Tf = 4940MHz (19)
    {0x0D, 0x55, 0x51}, // channel = 189, Tf = 4945MHz (20)
    {0x15, 0x55, 0x51}, // channel = 192, Tf = 4960MHz (21)
    {0x00, 0x00, 0x01}, // channel = 196, Tf = 4980MHz (22)

    // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 
    // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    {0x1D, 0x55, 0x51}, // channel =   7, Tf = 5035MHz (23)
    {0x00, 0x00, 0x01}, // channel =   8, Tf = 5040MHz (24)
    {0x02, 0xAA, 0xA1}, // channel =   9, Tf = 5045MHz (25)
    {0x08, 0x00, 0x01}, // channel =  11, Tf = 5055MHz (26)
    {0x0A, 0xAA, 0xA1}, // channel =  12, Tf = 5060MHz (27)
    {0x15, 0x55, 0x51}, // channel =  16, Tf = 5080MHz (28)
    {0x05, 0x55, 0x51}, // channel =  34, Tf = 5170MHz (29)
    {0x0A, 0xAA, 0xA1}, // channel =  36, Tf = 5180MHz (30)
    {0x10, 0x00, 0x01}, // channel =  38, Tf = 5190MHz (31)
    {0x15, 0x55, 0x51}, // channel =  40, Tf = 5200MHz (32)
    {0x1A, 0xAA, 0xA1}, // channel =  42, Tf = 5210MHz (33)
    {0x00, 0x00, 0x01}, // channel =  44, Tf = 5220MHz (34)
    {0x05, 0x55, 0x51}, // channel =  46, Tf = 5230MHz (35)
    {0x0A, 0xAA, 0xA1}, // channel =  48, Tf = 5240MHz (36)
    {0x15, 0x55, 0x51}, // channel =  52, Tf = 5260MHz (37)
    {0x00, 0x00, 0x01}, // channel =  56, Tf = 5280MHz (38)
    {0x0A, 0xAA, 0xA1}, // channel =  60, Tf = 5300MHz (39)
    {0x15, 0x55, 0x51}, // channel =  64, Tf = 5320MHz (40)
    {0x15, 0x55, 0x51}, // channel = 100, Tf = 5500MHz (41)