rtmp.h
来自「Ralink RT61 SoftAP Driver source code. 」· C头文件 代码 · 共 1,769 行 · 第 1/5 页
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1,769 行
/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2005, Ralink Technology, Inc.
*
* All rights reserved. Ralink's source code is an unpublished work and the
* use of a copyright notice does not imply otherwise. This source code
* contains confidential trade secret material of Ralink Tech. Any attempt
* or participation in deciphering, decoding, reverse engineering or in any
* way altering the source code is stricitly prohibited, unless the prior
* written consent of Ralink Technology, Inc. is obtained.
***************************************************************************
Module Name:
rtmp.h
Abstract:
Miniport generic portion header file
Revision History:
Who When What
-------- ---------- ----------------------------------------------
Paul Lin 2002-08-01 created
James Tan 2002-09-06 modified (Revise NTCRegTable)
John Chang 2004-09-06 modified for RT2600
*/
#ifndef __RTMP_H__
#define __RTMP_H__
#include "mlme.h"
#include "oid.h"
#ifdef APCLI_SUPPORT
#include "sta_mlme.h"
#endif
//
// Queue structure and macros
//
typedef struct _QUEUE_ENTRY {
struct _QUEUE_ENTRY *Next;
} QUEUE_ENTRY, *PQUEUE_ENTRY;
// Queue structure
typedef struct _QUEUE_HEADER {
PQUEUE_ENTRY Head;
PQUEUE_ENTRY Tail;
ULONG Number;
} QUEUE_HEADER, *PQUEUE_HEADER;
#define InitializeQueueHeader(QueueHeader) \
{ \
(QueueHeader)->Head = (QueueHeader)->Tail = NULL; \
(QueueHeader)->Number = 0; \
}
#define RemoveHeadQueue(QueueHeader) \
(QueueHeader)->Head; \
{ \
PQUEUE_ENTRY pNext; \
if ((QueueHeader)->Head != NULL) \
{ \
pNext = (QueueHeader)->Head->Next; \
(QueueHeader)->Head = pNext; \
if (pNext == NULL) \
(QueueHeader)->Tail = NULL; \
(QueueHeader)->Number--; \
} \
}
#define InsertHeadQueue(QueueHeader, QueueEntry) \
{ \
((PQUEUE_ENTRY)QueueEntry)->Next = (QueueHeader)->Head; \
(QueueHeader)->Head = (PQUEUE_ENTRY)(QueueEntry); \
if ((QueueHeader)->Tail == NULL) \
(QueueHeader)->Tail = (PQUEUE_ENTRY)(QueueEntry); \
(QueueHeader)->Number++; \
}
#define InsertTailQueue(QueueHeader, QueueEntry) \
{ \
((PQUEUE_ENTRY)QueueEntry)->Next = NULL; \
if ((QueueHeader)->Tail) \
(QueueHeader)->Tail->Next = (PQUEUE_ENTRY)(QueueEntry); \
else \
(QueueHeader)->Head = (PQUEUE_ENTRY)(QueueEntry); \
(QueueHeader)->Tail = (PQUEUE_ENTRY)(QueueEntry); \
(QueueHeader)->Number++; \
}
//
// MACRO for debugging information
//
#ifdef DBG
extern ULONG RTDebugLevel;
#define DBGPRINT(Level, fmt, args...) \
{ \
if (Level <= RTDebugLevel) \
{ \
printk(NIC_DBG_STRING); \
printk(KERN_DEBUG fmt, ## args); \
} \
}
#define DBGPRINT_ERR(fmt, args...) \
{ \
printk("ERROR!!! "); \
printk(KERN_DEBUG fmt, ## args);\
}
#else
#define DBGPRINT(Level, fmt, args...)
#define DBGPRINT_ERR(fmt, args...)
#endif
//
// spin_lock enhanced for Nested spin lock
//
#define NdisAllocateSpinLock(lock) \
{ \
spin_lock_init(lock); \
}
#define NdisFreeSpinLock(lock) \
{ \
}
#define RTMPFreeSkbBuffer(skb) \
{ \
dev_kfree_skb_any(skb); \
}
// Assert MACRO to make sure program running
//
#undef ASSERT
#define ASSERT(x) \
{ \
if (!(x)) \
{ \
printk(KERN_WARNING __FILE__ ":%d assert " #x "failed\n", __LINE__); \
} \
}
//
// Macros for flag and ref count operations
//
#define RTMP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
#define RTMP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
#define RTMP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
#define RTMP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
#define RTMP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
#define OPSTATUS_SET_FLAG(_pAd, _F) ((_pAd)->PortCfg.OpStatusFlags |= (_F))
#define OPSTATUS_CLEAR_FLAG(_pAd, _F) ((_pAd)->PortCfg.OpStatusFlags &= ~(_F))
#define OPSTATUS_TEST_FLAG(_pAd, _F) (((_pAd)->PortCfg.OpStatusFlags & (_F)) != 0)
#define CLIENT_STATUS_SET_FLAG(_pEntry,_F) ((_pEntry)->ClientStatusFlags |= (_F))
#define CLIENT_STATUS_CLEAR_FLAG(_pEntry,_F) ((_pEntry)->ClientStatusFlags &= ~(_F))
#define CLIENT_STATUS_TEST_FLAG(_pEntry,_F) (((_pEntry)->ClientStatusFlags & (_F)) != 0)
#define INC_RING_INDEX(_idx, _RingSize) \
{ \
(_idx)++; \
if ((_idx) >= (_RingSize)) _idx=0; \
}
// Increase TxTsc value for next transmission
// TODO:
// When i==6, means TSC has done one full cycle, do re-keying stuff follow specs
// Should send a special event microsoft defined to request re-key
#define INC_TX_TSC(_tsc) \
{ \
INT i=0; \
while (++_tsc[i] == 0x0) \
{ \
i++; \
if (i == 6) \
break; \
} \
}
#define NdisEqualMemory(Source1, Source2, Length) RTMPEqualMemory(Source1, Source2, Length)
//
// MACRO for 32-bit PCI register read / write
#if 0
#ifdef RTMP_EMBEDDED
#define RTMP_IO_READ32(_A, _R, _pV) (*_pV = PCIMemRead32(__mem_pci((_A)->CSRBaseAddress + (_R))))
#define RTMP_IO_WRITE32(_A, _R, _V) (PCIMemWrite32(__mem_pci((_A)->CSRBaseAddress + (_R)), _V))
#define RTMP_IO_WRITE8(_A, _R, _V) (PCIMemWrite8((PUCHAR)__mem_pci((_A)->CSRBaseAddress + (_R)), (_V)))
#define RTMP_IO_WRITE16(_A, _R, _V) (PCIMemWrite16((PUSHORT)__mem_pci((_A)->CSRBaseAddress + (_R)), (_V)))
#else
#define RTMP_IO_READ32(_A, _R, _pV) (*_pV = readl((void *)((_A)->CSRBaseAddress + (_R))))
#define RTMP_IO_WRITE32(_A, _R, _V) (writel(_V, (void *)((_A)->CSRBaseAddress + (_R))))
#define RTMP_IO_WRITE8(_A, _R, _V) (writeb((_V), (PUCHAR)((_A)->CSRBaseAddress + (_R))))
#define RTMP_IO_WRITE16(_A, _R, _V) (writew((_V), (PUSHORT)((_A)->CSRBaseAddress + (_R))))
#endif
#else
//Patch for ASIC turst read/write bug, needs to remove after metel fix
#define RTMP_IO_READ32(_A, _R, _pV) \
{ \
(*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \
(*_pV = readl((void *)((_A)->CSRBaseAddress + (_R)))); \
}
#define RTMP_IO_READ8(_A, _R, _pV) \
{ \
(*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \
(*_pV = readb((void *)((_A)->CSRBaseAddress + (_R)))); \
}
#define RTMP_IO_WRITE32(_A, _R, _V) \
{ \
ULONG Val; \
Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
writel(_V, (void *)((_A)->CSRBaseAddress + (_R))); \
}
#define RTMP_IO_WRITE8(_A, _R, _V) \
{ \
ULONG Val; \
Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
writeb((_V), (PUCHAR)((_A)->CSRBaseAddress + (_R))); \
}
#define RTMP_IO_WRITE16(_A, _R, _V) \
{ \
ULONG Val; \
Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
writew((_V), (PUSHORT)((_A)->CSRBaseAddress + (_R))); \
}
#endif
//
// BBP & RF are using indirect access. Before write any value into it.
// We have to make sure there is no outstanding command pending via checking busy bit.
//
#define MAX_BUSY_COUNT 100 // Number of retry before failing access BBP & RF indirect register
//
#define RTMP_RF_IO_WRITE32(_A, _V) \
{ \
PHY_CSR4_STRUC Value; \
ULONG BusyCnt = 0; \
do { \
RTMP_IO_READ32(_A, PHY_CSR4, &Value.word); \
if (Value.field.Busy == IDLE) \
break; \
BusyCnt++; \
} while (BusyCnt < MAX_BUSY_COUNT); \
if (BusyCnt < MAX_BUSY_COUNT) \
{ \
RTMP_IO_WRITE32(_A, PHY_CSR4, _V); \
} \
}
// Read BBP register by register's ID
#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
{ \
PHY_CSR3_STRUC BbpCsr; \
INT i, k; \
for (i=0; i<MAX_BUSY_COUNT; i++) \
{ \
RTMP_IO_READ32(_A, PHY_CSR3, &BbpCsr.word); \
if (BbpCsr.field.Busy == BUSY) \
{ \
continue; \
} \
BbpCsr.word = 0; \
BbpCsr.field.fRead = 1; \
BbpCsr.field.Busy = 1; \
BbpCsr.field.RegNum = _I; \
RTMP_IO_WRITE32(_A, PHY_CSR3, BbpCsr.word); \
for (k=0; k<MAX_BUSY_COUNT; k++) \
{ \
RTMP_IO_READ32(_A, PHY_CSR3, &BbpCsr.word); \
if (BbpCsr.field.Busy == IDLE) \
break; \
} \
if ((BbpCsr.field.Busy == IDLE) && \
(BbpCsr.field.RegNum == _I)) \
{ \
*(_pV) = (UCHAR)BbpCsr.field.Value; \
break; \
} \
} \
if (BbpCsr.field.Busy == BUSY) \
{ \
DBGPRINT_ERR("BBP read fail\n"); \
*(_pV) = (_A)->BbpWriteLatch[_I]; \
} \
}
// Write BBP register by register's ID & value
#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) \
{ \
PHY_CSR3_STRUC BbpCsr; \
INT BusyCnt; \
for (BusyCnt=0; BusyCnt<MAX_BUSY_COUNT; BusyCnt++) \
{ \
RTMP_IO_READ32(_A, PHY_CSR3, &BbpCsr.word); \
if (BbpCsr.field.Busy == BUSY) \
continue; \
BbpCsr.word = 0; \
BbpCsr.field.fRead = 0; \
BbpCsr.field.Busy = 1; \
BbpCsr.field.Value = _V; \
BbpCsr.field.RegNum = _I; \
RTMP_IO_WRITE32(_A, PHY_CSR3, BbpCsr.word); \
(_A)->BbpWriteLatch[_I] = _V; \
break; \
} \
}
// When write BBP r17, write the value to share memory at the same time
// Firmware will this value for radar detection
#define RTMP_WRITE_BBP_R17(_A, _V) \
{ \
ULONG BBPReg = 0x49112c10; \
\
RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, BBP_R17, _V); \
\
BBPReg = (BBPReg & 0x00FFFFFF) | (_V << 24); \
RTMP_IO_WRITE32(_A, 0x29bc, BBPReg); \
\
DBGPRINT(RT_DEBUG_INFO, "RTMP_WRITE_BBP_R17(BBPReg=%x)\n", BBPReg); \
\
}
#define NIC_MAX_PHYS_BUF_COUNT 8
typedef struct _RTMP_SCATTER_GATHER_ELEMENT {
PVOID Address;
ULONG Length;
PULONG Reserved;
} RTMP_SCATTER_GATHER_ELEMENT, *PRTMP_SCATTER_GATHER_ELEMENT;
typedef struct _RTMP_SCATTER_GATHER_LIST {
ULONG NumberOfElements;
PULONG Reserved;
RTMP_SCATTER_GATHER_ELEMENT Elements[NIC_MAX_PHYS_BUF_COUNT];
} RTMP_SCATTER_GATHER_LIST, *PRTMP_SCATTER_GATHER_LIST;
//
// Some utility macros
//
#ifndef min
#define min(_a, _b) (((_a) < (_b)) ? (_a) : (_b))
#endif
#ifndef max
#define max(_a, _b) (((_a) > (_b)) ? (_a) : (_b))
#endif
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