rtmp_init.c
来自「Ralink RT61 SoftAP Driver source code. 」· C语言 代码 · 共 1,988 行 · 第 1/5 页
C
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/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2005, Ralink Technology, Inc.
*
* All rights reserved. Ralink's source code is an unpublished work and the
* use of a copyright notice does not imply otherwise. This source code
* contains confidential trade secret material of Ralink Tech. Any attempt
* or participation in deciphering, decoding, reverse engineering or in any
* way altering the source code is stricitly prohibited, unless the prior
* written consent of Ralink Technology, Inc. is obtained.
***************************************************************************
Module Name:
rtmp_init.c
Abstract:
Miniport generic portion header file
Revision History:
Who When What
-------- ---------- ----------------------------------------------
Paul Lin 2002-08-01 created
John Chang 2004-08-20 RT2561/2661 use scatter-gather scheme
*/
#include "rt_config.h"
UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
ULONG BIT32[] = {0x00000001, 0x00000002, 0x00000004, 0x00000008,
0x00000010, 0x00000020, 0x00000040, 0x00000080,
0x00000100, 0x00000200, 0x00000400, 0x00000800,
0x00001000, 0x00002000, 0x00004000, 0x00008000,
0x00010000, 0x00020000, 0x00040000, 0x00080000,
0x00100000, 0x00200000, 0x00400000, 0x00800000,
0x01000000, 0x02000000, 0x04000000, 0x08000000,
0x10000000, 0x20000000, 0x40000000, 0x80000000};
char* CipherName[] = {"none","wep64","wep128","TKIP","AES","CKIP64","CKIP128"};
const unsigned short ccitt_16Table[] = {
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
};
#define ByteCRC16(v, crc) \
(unsigned short)((crc << 8) ^ ccitt_16Table[((crc >> 8) ^ (v)) & 255])
//
// BBP register initialization set
//
BBP_REG_PAIR BBPRegTable[] = {
{3, 0x00},
{15, 0x30},
{17, 0x40},
{21, 0xc8},
{22, 0x38},
{23, 0x06},
{24, 0xfe},
{25, 0x0a},
{26, 0x0d},
{34, 0x12},
{37, 0x07},
{39, 0xf8}, // 2005-09-02 by Gary, Atheros 11b issue
{41, 0x60},
{53, 0x10},
{54, 0x18},
{60, 0x10},
{61, 0x04},
{62, 0x04},
{75, 0xfe},
{86, 0xfe},
{88, 0xfe},
{90, 0x0f},
{99, 0x00},
{102, 0x16},
{107, 0x04},
};
#define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(BBP_REG_PAIR))
//
// ASIC register initialization sets
//
RTMP_REG_PAIR MACRegTable[] = {
// {MAC_CSR11, 0x0000000a}, // 0x302c, power state transition time
// {TXRX_CSR5, 0x0000000f}, // 0x3054, Basic rate set bitmap
// {TXRX_CSR0, 0x0277b032}, // 0x3040, RX control
{TXRX_CSR1, 0x9eb39eb3}, // 0x3044, BBP 51:RSSI, R42:OFDM rate, R47:CCK SIGNAL
{TXRX_CSR2, 0x8a8b8c8d}, // 0x3048, CCK TXD BBP registers
{TXRX_CSR3, 0x00858687}, // 0x304c, OFDM TXD BBP registers
{TXRX_CSR4, 0xf44a0732}, // 0x3050, Auto Responder / TX retransmission register
{TXRX_CSR7, 0x2E31353B}, // 0x305c, ACK/CTS payload consume time for 18/12/9/6 mbps
{TXRX_CSR8, 0x2a2a2a2c}, // 0x3060, ACK/CTS payload consume time for 54/48/36/24 mbps
{TXRX_CSR15, 0x0000000f}, // 0x307c, TKIP MIC priority byte "AND" mask
{MAC_CSR6, 0x00000fff}, // 0x3018, MAX frame length
{MAC_CSR10, 0x00000718}, // 0x3028, ASIC PIN control in various power states
{MAC_CSR12, 0x00000004}, // 0x3030, power state control, set to AWAKE state
{MAC_CSR13, 0x0000fe00}, // 0x3034, GPIO pin#0 as bHwRadio
// {INT_SOURCE_CSR,0xffffffff}, // 0x3068, Clear all pending interrupt source
// {MAC_CSR14, 0x00001e6}, // 0x3038, default both LEDs off
// {PHY_CSR2, 0x82188200}, // 0x308c, pre-TX BBP control
// {TXRX_CSR11, 0x0000e78f}, // 0x306c, AES, mask off more data bit for MIC calculation
// {TX_DMA_DST_CSR,0x000000aa}, // 0x342c, ASIC TX FIFO to host shared memory mapping
{SEC_CSR0, 0x00000000}, // 0x30a0, invalidate all shared key entries
{SEC_CSR1, 0x00000000}, // 0x30a4, reset all shared key algorithm to "none"
{SEC_CSR5, 0x00000000}, // 0x30b4, reset all shared key algorithm to "none"
{PHY_CSR5, 0x060a100c}, // 0x00040a06
{PHY_CSR6, 0x00080606},
{PHY_CSR7, 0x00000a08},
{PCI_CFG_CSR, 0x28ca4404}, // 0x3460, PCI configuration (old value will cause DMA issue, modified by Mark Liu)
{AIFSN_CSR, 0x00002273},
{CWMIN_CSR, 0x00002344},
{CWMAX_CSR, 0x000034aa},
{MAC_CSR8, 0x016c030a}, // 0x3020, SIFS time for compensation
{PHY_CSR1, 0x000023b0}, // 0x3084, BBP Register R/W mode set to "Parallel mode"
//{TEST_MODE_CSR, 0x00000200}, // 0x3484, Count TXOP anyway. by Mark 2005/07/27 for WMM S3T07 issue
{M2H_CMD_DONE_CSR, 0xffffffff}, // 0x2104, clear M2H_CMD_DONE mailbox
};
#define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR))
/*
========================================================================
Routine Description:
Allocate RTMP_ADAPTER data block and do some initialization
Arguments:
Adapter Pointer to our adapter
Return Value:
NDIS_STATUS_SUCCESS
NDIS_STATUS_FAILURE
Note:
========================================================================
*/
NDIS_STATUS RTMPAllocAdapterBlock(
IN PRTMP_ADAPTER pAdapter)
{
DBGPRINT(RT_DEBUG_TRACE, "--> RTMPAllocAdapterBlock\n");
do
{
// Init spin locks
NdisAllocateSpinLock(&pAdapter->TxRingLock);
NdisAllocateSpinLock(&pAdapter->MgmtRingLock);
NdisAllocateSpinLock(&pAdapter->RxRingLock);
NdisAllocateSpinLock(&pAdapter->TxSwQueueLock);
} while (FALSE);
DBGPRINT(RT_DEBUG_TRACE, "<-- RTMPAllocAdapterBlock\n");
return (NDIS_STATUS_SUCCESS);
}
/*
========================================================================
Routine Description:
Allocate all DMA releated resources
Arguments:
Adapter Pointer to our adapter
Return Value:
None
Note:
========================================================================
*/
NDIS_STATUS RTMPAllocDMAMemory(
IN PRTMP_ADAPTER pAdapter)
{
ULONG RingBasePa;
PVOID RingBaseVa;
INT index, num;
PTXD_STRUC pTxD;
PRXD_STRUC pRxD;
PRTMP_TX_RING pTxRing;
PRTMP_DMABUF pDmaBuf;
struct sk_buff *pSkb;
DBGPRINT(RT_DEBUG_TRACE, "--> RTMPAllocDMAMemory\n");
do
{
//
// Allocate all ring descriptors, include TxD, RxD, MgmtD.
// Although each size is different, to prevent cacheline and alignment
// issue, I intentional set them all to 64 bytes.
//
for (num=0; num<NUM_OF_TX_RING; num++)
{
ULONG BufBasePaLow;
PVOID BufBaseVa;
//
// Allocate Tx ring descriptor's memory (5 TX rings = 4 ACs + 1 HCCA)
//
pAdapter->TxDescRing[num].AllocSize = TX_RING_SIZE * TXD_SIZE;
pAdapter->TxDescRing[num].AllocVa
= pci_alloc_consistent(pAdapter->pPci_Dev, pAdapter->TxDescRing[num].AllocSize, &pAdapter->TxDescRing[num].AllocPa);
if (pAdapter->TxDescRing[num].AllocVa == NULL)
{
DBGPRINT_ERR("Failed to allocate a big buffer\n");
break;
}
// Zero init this memory block
NdisZeroMemory(pAdapter->TxDescRing[num].AllocVa, pAdapter->TxDescRing[num].AllocSize);
// Save PA & VA for further operation
RingBasePa = pAdapter->TxDescRing[num].AllocPa;
RingBaseVa = pAdapter->TxDescRing[num].AllocVa;
//
// Allocate all 1st TXBuf's memory for this TxRing
//
pAdapter->TxBufSpace[num].AllocSize = TX_RING_SIZE * TX_DMA_1ST_BUFFER_SIZE;
pAdapter->TxBufSpace[num].AllocVa
= pci_alloc_consistent(pAdapter->pPci_Dev, pAdapter->TxBufSpace[num].AllocSize, &pAdapter->TxBufSpace[num].AllocPa);
if (pAdapter->TxBufSpace[num].AllocVa == NULL)
{
DBGPRINT_ERR("Failed to allocate a big buffer\n");
break;
}
// Zero init this memory block
NdisZeroMemory(pAdapter->TxBufSpace[num].AllocVa, pAdapter->TxBufSpace[num].AllocSize);
// Save PA & VA for further operation
BufBasePaLow = pAdapter->TxBufSpace[num].AllocPa;
BufBaseVa = pAdapter->TxBufSpace[num].AllocVa;
//
// Initialize Tx Ring Descriptor and associated buffer memory
//
pTxRing = &pAdapter->TxRing[num];
for (index = 0; index < TX_RING_SIZE; index++)
{
// Init Tx Ring Size, Va, Pa variables
pTxRing->Cell[index].AllocSize = TXD_SIZE;
pTxRing->Cell[index].AllocVa = RingBaseVa;
pTxRing->Cell[index].AllocPa = RingBasePa;
// Setup Tx Buffer size & address. only 802.11 header will store in this space
pDmaBuf = &pTxRing->Cell[index].DmaBuf;
pDmaBuf->AllocSize = TX_DMA_1ST_BUFFER_SIZE;
pDmaBuf->AllocVa = BufBaseVa;
pDmaBuf->AllocPa = BufBasePaLow;
// link the pre-allocated TxBuf to TXD
pTxD = (PTXD_STRUC) pTxRing->Cell[index].AllocVa;
pTxD->BufCount = 1;
pTxD->BufPhyAddr0 = BufBasePaLow;
#ifdef BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
// advance to next ring descriptor address
RingBasePa += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
// advance to next TxBuf address
BufBasePaLow += TX_DMA_1ST_BUFFER_SIZE;
BufBaseVa = (PUCHAR) BufBaseVa + TX_DMA_1ST_BUFFER_SIZE;
}
DBGPRINT(RT_DEBUG_TRACE, "TxRing[%d]: total %d entry allocated\n", num, index);
}
//
// Allocate MGMT ring descriptor's memory except Tx ring which allocated eariler
//
pAdapter->MgmtDescRing.AllocSize = MGMT_RING_SIZE * TXD_SIZE;
pAdapter->MgmtDescRing.AllocVa
= pci_alloc_consistent(pAdapter->pPci_Dev, pAdapter->MgmtDescRing.AllocSize, &pAdapter->MgmtDescRing.AllocPa);
if (pAdapter->MgmtDescRing.AllocVa == NULL)
{
DBGPRINT_ERR("Failed to allocate a big buffer\n");
break;
}
// Zero init this memory block
NdisZeroMemory(pAdapter->MgmtDescRing.AllocVa, pAdapter->MgmtDescRing.AllocSize);
// Save PA & VA for further operation
RingBasePa = pAdapter->MgmtDescRing.AllocPa;
RingBaseVa = pAdapter->MgmtDescRing.AllocVa;
//
// Initialize MGMT Ring and associated buffer memory
//
for (index = 0; index < MGMT_RING_SIZE; index++)
{
// Init MGMT Ring Size, Va, Pa variables
pAdapter->MgmtRing.Cell[index].AllocSize = TXD_SIZE;
pAdapter->MgmtRing.Cell[index].AllocVa = RingBaseVa;
pAdapter->MgmtRing.Cell[index].AllocPa = RingBasePa;
// Offset to next ring descriptor address
RingBasePa += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
// no pre-allocated buffer required in MgmtRing for scatter-gather case
}
DBGPRINT(RT_DEBUG_TRACE, "MGMT Ring: total %d entry allocated\n", index);
//
// Allocate RX ring descriptor's memory except Tx ring which allocated eariler
//
pAdapter->RxDescRing.AllocSize = RX_RING_SIZE * RXD_SIZE;
pAdapter->RxDescRing.AllocVa
= pci_alloc_consistent(pAdapter->pPci_Dev, pAdapter->RxDescRing.AllocSize, &pAdapter->RxDescRing.AllocPa);
if (pAdapter->RxDescRing.AllocVa == NULL)
{
DBGPRINT_ERR("Failed to allocate a big buffer\n");
break;
}
// Zero init this memory block
NdisZeroMemory(pAdapter->RxDescRing.AllocVa, pAdapter->RxDescRing.AllocSize);
// Save PA & VA for further operation
RingBasePa = pAdapter->RxDescRing.AllocPa;
RingBaseVa = pAdapter->RxDescRing.AllocVa;
//
// Initialize Rx Ring and associated buffer memory
//
for (index = 0; index < RX_RING_SIZE; index++)
{
// Init RX Ring Size, Va, Pa variables
pAdapter->RxRing.Cell[index].AllocSize = RXD_SIZE;
pAdapter->RxRing.Cell[index].AllocVa = RingBaseVa;
pAdapter->RxRing.Cell[index].AllocPa = RingBasePa;
// Offset to next ring descriptor address
RingBasePa += RXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + RXD_SIZE;
// Setup Rx associated Buffer size & allocate share memory
pDmaBuf = &pAdapter->RxRing.Cell[index].DmaBuf;
pDmaBuf->AllocSize = RX_DMA_BUFFER_SIZE;
pSkb = __dev_alloc_skb(pDmaBuf->AllocSize, MEM_ALLOC_FLAG);
RTMP_SET_PACKET_SOURCE(pSkb, PKTSRC_DRIVER);
pDmaBuf->pSkb = pSkb;
pDmaBuf->AllocVa = pSkb->data;
pDmaBuf->AllocPa = pci_map_single(pAdapter->pPci_Dev, (PVOID)pSkb->data, pDmaBuf->AllocSize, PCI_DMA_FROMDEVICE);
// Error handling
if (pDmaBuf->AllocVa == NULL)
{
DBGPRINT_ERR("Failed to allocate RxRing's 1st buffer\n");
break;
}
// Zero init this memory block
NdisZeroMemory(pDmaBuf->AllocVa, pDmaBuf->AllocSize);
// Write RxD buffer address & allocated buffer length
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