📄 rt2661.h
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// the above 24-byte is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
// The following fields are not used by MAC block. They are used by DMA block and HOST
// driver only. Once a frame has been DMA to ASIC, all the following fields are useless
// to ASIC.
// word 6~10
ULONG BufPhyAddr0;
ULONG BufPhyAddr1;
ULONG BufPhyAddr2;
ULONG BufPhyAddr3;
ULONG BufPhyAddr4;
// Word 11
ULONG Rsv5:4;
ULONG BufLen1:12;
ULONG Rsv4:4;
ULONG BufLen0:12;
// Word 12
ULONG Rsv7:4;
ULONG BufLen3:12;
ULONG Rsv6:4;
ULONG BufLen2:12;
// Word 13
ULONG Rsv9:16;
//ULONG TxRate:8; // for software usage only. record the TxRate
ULONG Rsv8:4;
ULONG BufLen4:12;
// Word 14
struct sk_buff *pSkb;
// Word 15
struct sk_buff *pNextSkb;
} TXD_STRUC, *PTXD_STRUC;
#else
typedef struct _TXD_STRUC {
// word 0
ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST
ULONG Drop:1; // 0: skip this frame, 1:valid frame inside
ULONG MoreFrag:1; // 1: More fragment following this frame
ULONG ACK:1; // 1: ACK is required
ULONG Timestamp:1; // 1: MAC auto overwrite current TSF into frame body
ULONG Ofdm:1; // 1: TX using OFDM rates
ULONG IFS:1; // 1: require a BACKOFF before this frame, 0:SIFS before this frame
ULONG RetryMd:1; // 1: Long retry (4 times), 0: short retry (7 times)
ULONG TkipMic:1; // 1: ASIC is responsible for appending TKIP MIC if TKIP is inused
ULONG KeyTable:1; // 1: use per-client pairwise KEY table, 0: shared KEY table
ULONG KeyIndex:6; // Key index (0~31) to the pairwise KEY table; or
// 0~3 to shared KEY table 0 (BSS0). STA always use BSS0
// 4~7 to shared KEY table 1 (BSS1)
// 8~11 to shared KEY table 2 (BSS2)
// 12~15 to shared KEY table 3 (BSS3)
ULONG DataByteCnt:12;
ULONG Burst:1; // 1: tell EDCA that the next frame belongs to the same "burst" even though TXOP=0
ULONG CipherAlg:3;
// Word 1
ULONG HostQId:4; // EDCA/HCCA queue ID
ULONG Aifsn:4;
ULONG Cwmin:4;
ULONG Cwmax:4;
ULONG IvOffset:6;
ULONG Rsv0:2;
ULONG PiggyBack:1;
ULONG Rsv1:3;
ULONG HwSeq:1; // MAC auto replace the 12-bit frame sequence #
ULONG BufCount:3; // number of buffers in this TXD
// Word 2
ULONG PlcpSignal:8;
ULONG PlcpService:8;
ULONG PlcpLengthLow:8;
ULONG PlcpLengthHigh:8;
// Word 3
ULONG Iv;
// Word 4
ULONG Eiv;
// Word 5
ULONG FrameOffset:8; // frame start offset inside ASIC TXFIFO (after TXINFO field)
ULONG PktId:8; // driver assigned packet ID to categorize TXResult in TxDoneInterrupt
ULONG BbpTxPower:8;
ULONG bWaitingDmaDoneInt:1; // pure s/w flag. 1:TXD been filled with data and waiting for TxDoneISR for housekeeping
ULONG :7;
// the above 24-byte is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
// The following fields are not used by MAC block. They are used by DMA block and HOST
// driver only. Once a frame has been DMA to ASIC, all the following fields are useless
// to ASIC.
// word 6~10
ULONG BufPhyAddr0;
ULONG BufPhyAddr1;
ULONG BufPhyAddr2;
ULONG BufPhyAddr3;
ULONG BufPhyAddr4;
// Word 11
ULONG BufLen0:12;
ULONG Rsv4:4;
ULONG BufLen1:12;
ULONG Rsv5:4;
// Word 12
ULONG BufLen2:12;
ULONG Rsv6:4;
ULONG BufLen3:12;
ULONG Rsv7:4;
// Word 13
ULONG BufLen4:12;
ULONG Rsv8:4;
//ULONG TxRate:8; // for software usage only. record the TxRate
ULONG Rsv9:16;
// Word 14
struct sk_buff *pSkb;
// Word 15
struct sk_buff *pNextSkb;
} TXD_STRUC, *PTXD_STRUC;
#endif
//
// Rx descriptor format, Rx Ring
//
#ifdef BIG_ENDIAN
typedef struct _RXD_STRUC {
// Word 0
ULONG CipherAlg:3;
ULONG Rsv:1;
ULONG DataByteCnt:12;
ULONG KeyIndex:6; // decryption key actually used
ULONG CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
// ULONG PhyErr:1; // 1: this frame is received with PHY error
ULONG Ofdm:1; // 1: this frame is received in OFDM rate
ULONG Crc:1; // 1: CRC error
ULONG MyBss:1; // 1: this frame belongs to the same BSSID
ULONG Bcast:1; // 1: this is a broadcast frame
ULONG Mcast:1; // 1: this is a multicast frame
ULONG U2M:1; // 1: this RX frame is unicast to me
ULONG Drop:1; // 1: drop without receiving to HOST
ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST driver
// word 1
ULONG Rsv1:1;
ULONG FrameOffset:7;
ULONG Rsv0:8;
ULONG PlcpRssi:8; // RSSI reported by BBP
ULONG PlcpSignal:8; // RX raw data rate reported by BBP
// Word 2
ULONG Iv; // received IV if originally encrypted; for replay attack checking
// Word 3
ULONG Eiv; // received EIV if originally encrypted; for replay attack checking
// word 4
ULONG Rsv2;
// The above 20-byte is called RXINFO and is prepared by MAC RX block and passed
// the HOST driver.
// The following fields are for DMA block and HOST usage only. Can't be touched
// by ASIC MAC block.
// Word 5
ULONG BufPhyAddr;
// Word 6~15
ULONG Rsv3;
ULONG Rsv4;
ULONG Rsv5;
ULONG Rsv6;
ULONG Rsv7;
ULONG Rsv8;
ULONG Rsv9;
ULONG Rsv10;
ULONG Rsv11;
ULONG Rsv12;
} RXD_STRUC, *PRXD_STRUC;
#else
typedef struct _RXD_STRUC {
// Word 0
ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST driver
ULONG Drop:1; // 1: drop without receiving to HOST
ULONG U2M:1; // 1: this RX frame is unicast to me
ULONG Mcast:1; // 1: this is a multicast frame
ULONG Bcast:1; // 1: this is a broadcast frame
ULONG MyBss:1; // 1: this frame belongs to the same BSSID
ULONG Crc:1; // 1: CRC error
ULONG Ofdm:1; // 1: this frame is received in OFDM rate
// ULONG PhyErr:1; // 1: this frame is received with PHY error
ULONG CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
ULONG KeyIndex:6; // decryption key actually used
ULONG DataByteCnt:12;
ULONG Rsv:1;
ULONG CipherAlg:3;
// word 1
ULONG PlcpSignal:8; // RX raw data rate reported by BBP
ULONG PlcpRssi:8; // RSSI reported by BBP
ULONG Rsv0:8;
ULONG FrameOffset:7;
ULONG Rsv1:1;
// Word 2
ULONG Iv; // received IV if originally encrypted; for replay attack checking
// Word 3
ULONG Eiv; // received EIV if originally encrypted; for replay attack checking
// word 4
ULONG Rsv2;
// The above 20-byte is called RXINFO and is prepared by MAC RX block and passed
// the HOST driver.
// The following fields are for DMA block and HOST usage only. Can't be touched
// by ASIC MAC block.
// Word 5
ULONG BufPhyAddr;
// Word 6~15
ULONG Rsv3;
ULONG Rsv4;
ULONG Rsv5;
ULONG Rsv6;
ULONG Rsv7;
ULONG Rsv8;
ULONG Rsv9;
ULONG Rsv10;
ULONG Rsv11;
ULONG Rsv12;
} RXD_STRUC, *PRXD_STRUC;
#endif
// =================================================================================
// HOST-MCU communication data structure
// =================================================================================
//
// H2M_MAILBOX_CSR: Host-to-MCU Mailbox
//
#ifdef BIG_ENDIAN
typedef union _H2M_MAILBOX_STRUC {
struct {
ULONG Owner:8;
ULONG CmdToken:8; // 0xff tells MCU not to report CmdDoneInt after excuting the command
ULONG Arg1:8;
ULONG Arg0:8;
} field;
ULONG word;
} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
#else
typedef union _H2M_MAILBOX_STRUC {
struct {
ULONG Arg0:8;
ULONG Arg1:8;
ULONG CmdToken:8;
ULONG Owner:8;
} field;
ULONG word;
} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
#endif
//
// M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
//
#ifdef BIG_ENDIAN
typedef union _M2H_CMD_DONE_STRUC {
struct {
ULONG CmdToken3;
ULONG CmdToken2;
ULONG CmdToken1;
ULONG CmdToken0;
} field;
ULONG word;
} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
#else
typedef union _M2H_CMD_DONE_STRUC {
struct {
ULONG CmdToken0;
ULONG CmdToken1;
ULONG CmdToken2;
ULONG CmdToken3;
} field;
ULONG word;
} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
#endif
//
// MCU_INT_SOURCE_CSR, MCU_INT_MASK_CSR: MCU interrupt source/mask register
//
#ifdef BIG_ENDIAN
typedef union _MCU_INT_SOURCE_STRUC {
struct {
ULONG :22;
ULONG TBTTExpire:1;
ULONG Twakeup:1;
ULONG McuInt7:1;
ULONG McuInt6:1;
ULONG McuInt5:1;
ULONG McuInt4:1;
ULONG McuInt3:1;
ULONG McuInt2:1;
ULONG McuInt1:1;
ULONG McuInt0:1;
} field;
ULONG word;
} MCU_INT_SOURCE_STRUC, *PMCU_INT_SOURCE_STRUC, MCU_INT_MASK_STRUC, *PMCU_INT_MASK_STRUC;
#else
typedef union _MCU_INT_SOURCE_STRUC {
struct {
ULONG McuInt0:1;
ULONG McuInt1:1;
ULONG McuInt2:1;
ULONG McuInt3:1;
ULONG McuInt4:1;
ULONG McuInt5:1;
ULONG McuInt6:1;
ULONG McuInt7:1;
ULONG Twakeup:1;
ULONG TBTTExpire:1;
ULONG :22;
} field;
ULONG word;
} MCU_INT_SOURCE_STRUC, *PMCU_INT_SOURCE_STRUC, MCU_INT_MASK_STRUC, *PMCU_INT_MASK_STRUC;
#endif
//
// MCU_LEDCS: MCU LED Control Setting.
//
#ifdef BIG_ENDIAN
typedef union _MCU_LEDCS_STRUC {
struct {
USHORT PolarityRDY_A:1;
USHORT PolarityRDY_G:1;
USHORT PolarityACT:1;
USHORT PolarityGPIO_4:1;
USHORT PolarityGPIO_3:1;
USHORT PolarityGPIO_2:1;
USHORT PolarityGPIO_1:1;
USHORT PolarityGPIO_0:1;
USHORT LinkAStatus:1;
USHORT LinkGStatus:1;
USHORT RadioStatus:1;
USHORT LedMode:5;
} field;
USHORT word;
} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
#else
typedef union _MCU_LEDCS_STRUC {
struct {
USHORT LedMode:5;
USHORT RadioStatus:1;
USHORT LinkGStatus:1;
USHORT LinkAStatus:1;
USHORT PolarityGPIO_0:1;
USHORT PolarityGPIO_1:1;
USHORT PolarityGPIO_2:1;
USHORT PolarityGPIO_3:1;
USHORT PolarityGPIO_4:1;
USHORT PolarityACT:1;
USHORT PolarityRDY_G:1;
USHORT PolarityRDY_A:1;
} field;
USHORT word;
} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
#endif
// =================================================================================
// Register format
// =================================================================================
//
// MAC_CSR1: System control register
//
#ifdef BIG_ENDIAN
typedef union _MAC_CSR1_STRUC {
struct {
ULONG Rsvd1:29;
ULONG HostReady:1; // Host is ready after initialization, 1: ready
ULONG BbpReset:1; // Hardware reset BBP
ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
} field;
ULONG word;
} MAC_CSR1_STRUC, *PMAC_CSR1_STRUC;
#else
typedef union _MAC_CSR1_STRUC {
struct {
ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal
ULONG BbpReset:1; // Hardware reset BBP
ULONG HostReady:1; // Host is ready after initialization, 1: ready
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