📄 rt2661.h
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/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2005, Ralink Technology, Inc.
*
* All rights reserved. Ralink's source code is an unpublished work and the
* use of a copyright notice does not imply otherwise. This source code
* contains confidential trade secret material of Ralink Tech. Any attempt
* or participation in deciphering, decoding, reverse engineering or in any
* way altering the source code is stricitly prohibited, unless the prior
* written consent of Ralink Technology, Inc. is obtained.
***************************************************************************
Module Name:
rt2661.h
Abstract:
RT2561/2661 ASIC related definition & structures
Revision History:
Who When What
-------- ---------- ----------------------------------------------
John Chang Aug-16-2004 created for RT2561/2661
John Chang Nov-08-2004 change as MAC register spec v0.92 (2004-10-26)
*/
#ifndef __RT2661_H__
#define __RT2661_H__
//
// PCI registers - base address 0x0000
//
#define HOST_CMD_CSR 0x0008
#define MCU_CNTL_CSR 0x000c
#define SOFT_RESET_CSR 0x0010
#define MCU_INT_SOURCE_CSR 0x0014
#define MCU_INT_MASK_CSR 0x0018
#define PCI_USEC_CSR 0x001c
//
// Security key table memory, base address = 0x1000
//
#define SHARED_KEY_TABLE_BASE 0x1000 // 32-byte * 16-entry = 512-byte
#define PAIRWISE_KEY_TABLE_BASE 0x1200 // 32-byte * 64-entry = 2048-byte
#define PAIRWISE_TA_TABLE_BASE 0x1a00 // 8-byte * 64-entry = 512-byte
// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
typedef struct _HW_KEY_ENTRY { // 32-byte per entry
UCHAR Key[16];
UCHAR TxMic[8];
UCHAR RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY;
#define HW_KEY_ENTRY_SIZE sizeof(HW_KEY_ENTRY)
// 64-entry for pairwise key table
typedef struct _HW_PAIRWISE_TA_ENTRY { // 8-byte per entry
UCHAR Address[6];
UCHAR Rsv[2];
} HW_PAIRWISE_TA_ENTRY, PHW_PAIRWISE_TA_ENTRY;
#define HW_PAIRWISE_TA_ENTRY_SIZE sizeof(HW_PAIRWISE_TA_ENTRY)
//
// Other on-chip shared memory space, base = 0x2000
//
// CIS space - base address = 0x2000
#define HW_CIS_BASE 0x2000
// on-chip CTS frame space - base address = 0x2a00
#define HW_CTS_FRAME_BASE 0x2a00
#define HW_CTS_FRAME_SIZE 0x80
// on-chip NULL frame space - base address = 0x2b00
#define HW_NULL_BASE 0x2b00
// 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
// to save debugging settings
#define HW_DEBUG_SETTING_BASE 0x2bf0 // 0x2bf0~0x2bff total 16 bytes
// on-chip BEACON frame space - base address = 0x2c00
#define HW_BEACON_BASE0 0x2c00
#define HW_BEACON_BASE1 0x2d00
#define HW_BEACON_BASE2 0x2e00
#define HW_BEACON_BASE3 0x2f00
#define HW_BEACON_OFFSET 0x100
// HOST-MCU shared memory - base address = 0x2100
#define H2M_MAILBOX_CSR 0x2100
#define M2H_CMD_DONE_CSR 0x2104
#define MCU_TXOP_ARRAY_BASE 0x2110 // TODO: to be provided by Albert
#define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
#define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
#define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
#define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
//
// MAC Control Registers - base address 0x3000
//
#define MAC_CSR0 0x3000
#define MAC_CSR1 0x3004
#define MAC_CSR2 0x3008
#define MAC_CSR3 0x300c
#define MAC_CSR4 0x3010
#define MAC_CSR5 0x3014
#define MAC_CSR6 0x3018
#define MAC_CSR7 0x301c
#define MAC_CSR8 0x3020 // SIFS/EIFS
#define MAC_CSR9 0x3024
#define MAC_CSR10 0x3028 // power state configuration
#define MAC_CSR11 0x302c // Power state transition time
#define MAC_CSR12 0x3030 // power state
#define MAC_CSR13 0x3034 // GPIO
#define MAC_CSR14 0x3038 // LED control
#define MAC_CSR15 0x303c // NAV control
//
// TXRX control registers - base address 0x3000
//
#define TXRX_CSR0 0x3040
#define TXRX_CSR1 0x3044
#define TXRX_CSR2 0x3048
#define TXRX_CSR3 0x304c
#define TXRX_CSR4 0x3050
#define TXRX_CSR5 0x3054
#define TXRX_CSR6 0x3058 // ACK/CTS payload consumed time
#define TXRX_CSR7 0x305c // ACK/CTS payload consumed time
#define TXRX_CSR8 0x3060 // ACK/CTS payload consumed time
#define TXRX_CSR9 0x3064 // BEACON SYNC
#define TXRX_CSR10 0x3068 // BEACON alignment
#define TXRX_CSR11 0x306c // AES mask
#define TXRX_CSR12 0x3070 // TSF low 32
#define TXRX_CSR13 0x3074 // TSF high 32
#define TXRX_CSR14 0x3078 // TBTT timer
#define TXRX_CSR15 0x307c // TKIP MIC priority byte "AND" mask
//
// PHY control registers - base address 0x3000
//
#define PHY_CSR0 0x3080 // RF/PS control
#define PHY_CSR1 0x3084
#define PHY_CSR2 0x3088 // pre-TX BBP control
#define PHY_CSR3 0x308c // BBP access
#define PHY_CSR4 0x3090 // RF serial control
#define PHY_CSR5 0x3094 // RX to TX signal switch timing control
#define PHY_CSR6 0x3098 // TX to RX signal timing control
#define PHY_CSR7 0x309c // TX DAC switching timing control
//
// Security control register - base address 0x3000
//
#define SEC_CSR0 0x30a0 // shared key table control
#define SEC_CSR1 0x30a4 // shared key table security mode
#define SEC_CSR2 0x30a8 // pairwise key table valid bitmap 0
#define SEC_CSR3 0x30ac // pairwise key table valid bitmap 1
#define SEC_CSR4 0x30b0 // pairwise key table lookup control
#define SEC_CSR5 0x30b4 // shared key table security mode
//
// STA control registers - base address 0x3000
//
#define STA_CSR0 0x30c0 // CRC/PLCP error counter
#define STA_CSR1 0x30c4 // Long/False-CCA error counter
#define STA_CSR2 0x30c8 // RX FIFO overflow counter
#define STA_CSR3 0x30cc // TX Beacon counter
#define STA_CSR4 0x30d0 // TX Status Queue
//
// QOS control registers - base address 0x3000
//
#define QOS_CSR0 0x30e0 // TXOP holder MAC address 0
#define QOS_CSR1 0x30e4 // TXOP holder MAC address 1
#define QOS_CSR2 0x30e8 // TXOP holder timeout register
#define QOS_CSR3 0x30ec // RX QOS-CFPOLL MAC address 0
#define QOS_CSR4 0x30f0 // RX QOS-CFPOLL MAC address 1
#define QOS_CSR5 0x30f4 // "QosControl" field of the RX QOS-CFPOLL
//
// Host DMA registers - base address 0x3400
//
#define AC0_BASE_CSR 0x3400 // AC_BK base address
#define AC1_BASE_CSR 0x3404 // AC_BE base address
#define AC2_BASE_CSR 0x3408 // AC_VI base address
#define AC3_BASE_CSR 0x340c // AC_VO base address
#define MGMT_BASE_CSR 0x3410 // MGMT ring base address
#define TX_RING_CSR0 0x3418
#define TX_RING_CSR1 0x341c
#define AIFSN_CSR 0x3420
#define CWMIN_CSR 0x3424
#define CWMAX_CSR 0x3428
#define TX_DMA_DST_CSR 0x342c
#define TX_CNTL_CSR 0x3430 // kick/abort TX
#define LOAD_TX_RING_CSR 0x3434
#define AC0_TXPTR_CSR 0x3438 // read-only, for debugging
#define AC1_TXPTR_CSR 0x343c // read-only, for debugging
#define AC2_TXPTR_CSR 0x3440 // read-only, for debugging
#define AC3_TXPTR_CSR 0x3444 // read-only, for debugging
#define MGMT_TXPTR_CSR 0x3448 // read-only, for debugging
#define RX_BASE_CSR 0x3450
#define RX_RING_CSR 0x3454
#define RX_CNTL_CSR 0x3458
#define RXPTR_CSR 0x345c // read-only, for debugging
#define PCI_CFG_CSR 0x3460
#define BUF_FORMAT_CSR 0x3464
#define INT_SOURCE_CSR 0x3468
#define INT_MASK_CSR 0x346c
#define E2PROM_CSR 0x3470
#define AC_TXOP_CSR0 0x3474
#define AC_TXOP_CSR1 0x3478
#define DMA_STATUS_CSR 0x3480
#define TEST_MODE_CSR 0x3484
#define UART0_TX_CSR 0x3488
#define UART0_RX_CSR 0x348c
#define UART0_FRAME_CSR 0x3490
#define UART0_BUFFER_CSR 0x3494
#define IO_CNTL_CSR 0x3498
#define UART_INT_SOURCE_CSR 0x34a8
#define UART_INT_MASK_CSR 0x34ac
#define PBF_QUEUE_CSR 0x34b0
// firmware DMA registers - base 0x3400
// firmwre DMA registers are dedicated for MCU usage and should not be touched
// by host driver. Therefore we skip the definition of these registers
#define FW_TX_BASE_CSR 0x34c0
#define FW_TX_START_CSR 0x34c4
#define FW_TX_LAST_CSR 0x34c8
#define FW_MODE_CNTL_CSR 0x34cc
#define FW_TXPTR_CSR 0x34d0
// 8051 firmware image - base address = 0x4000
#define FIRMWARE_IMAGE_BASE 0x4000
#define MAX_FIRMWARE_IMAGE_SIZE 8192 // 8kbyte
// ================================================================
// Tx / Rx / Mgmt ring descriptor definition
// ================================================================
// value domain of pTxD->Owner and pRxD->Owner
#define DESC_OWN_HOST 0
#define DESC_OWN_NIC 1
// the following PID values are used to mark outgoing frame type in TXD so that
// proper TX statistics can be collected based on these categories
#define PTYPE_DATA_REQUIRE_ACK 0x00 // b7-6:00, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
#define PTYPE_NULL_AT_HIGH_RATE 0x40 // b7-6:01, b5-0: 0~59 is MAC table index (AID?), 60~63 is WDS index
#define PTYPE_RESERVED 0x80 // b7-6:10
#define PTYPE_SPECIAL 0xc0 // b7-6:11
#define PSUBTYPE_DATA_NO_ACK 0x00
#define PSUBTYPE_MGMT 0x01
#define PSUBTYPE_OTHER_CNTL 0x02
#define PSUBTYPE_RTS 0x03
#define PSUBTYPE_MCU_INTERNAL 0x04
// value domain of pTxD->HostQId (4-bit: 0~15)
#define QID_AC_BK 1 // meet ACI definition in 802.11e
#define QID_AC_BE 0 // meet ACI definition in 802.11e
#define QID_AC_VI 2
#define QID_AC_VO 3
#define QID_HCCA 4
#define NUM_OF_TX_RING 5
#define QID_MGMT 13
#define QID_RX 14
#define QID_OTHER 15
// ------------------------------------------------------
// BBP & RF definition
// ------------------------------------------------------
#define BUSY 1
#define IDLE 0
#define BBP_R0 0 // version
#define BBP_R1 1 // TSSI
#define BBP_R2 2 // TX configure
#define BBP_R3 3
#define BBP_R4 4
#define BBP_R5 5
#define BBP_R6 6
#define BBP_R14 14 // RX configure
#define BBP_R16 16
#define BBP_R17 17 // RX sensibility
#define BBP_R18 18
#define BBP_R21 21
#define BBP_R22 22
#define BBP_R62 62 // Rx SQ0 Threshold HIGH
#define BBP_R64 64
#define BBP_R66 66
#define BBP_R67 67
#define BBP_R68 68
#define BBP_R69 69
#define BBP_R75 75
#define BBP_R70 70 // Japan filter
#define BBP_R77 77
#define BBP_R82 82
#define BBP_R83 83
#define BBP_R84 84
#define BBP_R86 86
#define BBP_R88 88
#define BBP_R94 94 // Tx Gain Control
#define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
#define RSSI_FOR_LOW_SENSIBILITY -58
#define RSSI_FOR_MID_SENSIBILITY -78
//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO 0x10
#define EEDI 0x08
#define EECS 0x04
#define EESK 0x02
#define EERL 0x01
#define EEPROM_WRITE_OPCODE 0x05
#define EEPROM_READ_OPCODE 0x06
#define EEPROM_EWDS_OPCODE 0x10
#define EEPROM_EWEN_OPCODE 0x13
#define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
#define NUM_EEPROM_TX_G_PARMS 7
#define EEPROM_BBP_BASE_OFFSET 0x20 // The address is from NIC config 0, not BBP register ID
#define EEPROM_G_TX_PWR_OFFSET 0x46
#define EEPROM_LED_OFFSET 0x60
#define EEPROM_A_TX_PWR_OFFSET 0x62
//#define EEPROM_TSSI_REF_OFFSET 0x54
//#define EEPROM_TSSI_DELTA_OFFSET 0x24
//#define EEPROM_CCK_TX_PWR_OFFSET 0x62
//#define EEPROM_CALIBRATE_OFFSET 0x7c
#define EEPROM_VERSION_OFFSET 0x02
#define EEPROM_FREQ_OFFSET 0x5e
#define EEPROM_RSSI_BG_OFFSET 0x9A
#define EEPROM_RSSI_A_OFFSET 0x9C
#define EEPROM_TX_POWER_DELTA 0x9E
#define VALID_EEPROM_VERSION 1
// =================================================================================
// TX / RX ring descriptor format
// =================================================================================
// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
// MAC block use this TXINFO to control the transmission behavior of this frame.
#define TXINFO_SIZE 24
//
// TX descriptor format, Tx ring, Mgmt Ring
//
#ifdef BIG_ENDIAN
typedef struct _TXD_STRUC {
// word 0
ULONG CipherAlg:3;
ULONG Burst:1; // 1: tell EDCA that the next frame belongs to the same "burst" even though TXOP=0
ULONG DataByteCnt:12;
ULONG KeyIndex:6; // Key index (0~31) to the pairwise KEY table; or
// 0~3 to shared KEY table 0 (BSS0). STA always use BSS0
// 4~7 to shared KEY table 1 (BSS1)
// 8~11 to shared KEY table 2 (BSS2)
// 12~15 to shared KEY table 3 (BSS3)
ULONG KeyTable:1; // 1: use per-client pairwise KEY table, 0: shared KEY table
ULONG TkipMic:1; // 1: ASIC is responsible for appending TKIP MIC if TKIP is inused
ULONG RetryMd:1; // 1: Long retry (4 times), 0: short retry (7 times)
ULONG IFS:1; // 1: require a BACKOFF before this frame, 0:SIFS before this frame
ULONG Ofdm:1; // 1: TX using OFDM rates
ULONG Timestamp:1; // 1: MAC auto overwrite current TSF into frame body
ULONG ACK:1; // 1: ACK is required
ULONG MoreFrag:1; // 1: More fragment following this frame
ULONG Drop:1; // 0: skip this frame, 1:valid frame inside
ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST
// Word 1
ULONG BufCount:3; // number of buffers in this TXD
ULONG HwSeq:1; // MAC auto replace the 12-bit frame sequence #
ULONG Rsv1:3;
ULONG PiggyBack:1;
ULONG Rsv0:2;
ULONG IvOffset:6;
ULONG Cwmax:4;
ULONG Cwmin:4;
ULONG Aifsn:4;
ULONG HostQId:4; // EDCA/HCCA queue ID
// Word 2
ULONG PlcpLengthHigh:8;
ULONG PlcpLengthLow:8;
ULONG PlcpService:8;
ULONG PlcpSignal:8;
// Word 3
ULONG Iv;
// Word 4
ULONG Eiv;
// Word 5
ULONG :7;
ULONG bWaitingDmaDoneInt:1; // pure s/w flag. 1:TXD been filled with data and waiting for TxDoneISR for housekeeping
ULONG BbpTxPower:8;
ULONG PktId:8; // driver assigned packet ID to categorize TXResult in TxDoneInterrupt
ULONG FrameOffset:8; // frame start offset inside ASIC TXFIFO (after TXINFO field)
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