📄 ftc_fotg2xx.h
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//~A Function#define mdwOTGC_Control_A_BUS_REQ_Rd() (mdwFOTGPort(0x80)& BIT4)#define mdwOTGC_Control_A_BUS_REQ_Set() (mdwFOTGPort(0x80) |= BIT4)#define mdwOTGC_Control_A_BUS_REQ_Clr() (mdwFOTGPort(0x80) &= (~BIT4))#define mdwOTGC_Control_A_BUS_DROP_Rd() (mdwFOTGPort(0x80)& BIT5)#define mdwOTGC_Control_A_BUS_DROP_Set() (mdwFOTGPort(0x80) |= BIT5)#define mdwOTGC_Control_A_BUS_DROP_Clr() (mdwFOTGPort(0x80) &= (~BIT5))#define mdwOTGC_Control_A_SET_B_HNP_EN_Rd() (mdwFOTGPort(0x80)& BIT6)#define mdwOTGC_Control_A_SET_B_HNP_EN_Set() (mdwFOTGPort(0x80) |= BIT6)#define mdwOTGC_Control_A_SET_B_HNP_EN_Clr() (mdwFOTGPort(0x80) &= (~BIT6))#define mdwOTGC_Control_A_SRP_DET_EN_Rd() (mdwFOTGPort(0x80)& BIT7)#define mdwOTGC_Control_A_SRP_DET_EN_Set() (mdwFOTGPort(0x80) |= BIT7)#define mdwOTGC_Control_A_SRP_DET_EN_Clr() (mdwFOTGPort(0x80) &= (~BIT7))#define mdwOTGC_Control_A_SRP_RESP_TYPE_Rd() (mdwFOTGPort(0x80)& BIT8)#define mdwOTGC_Control_A_SRP_RESP_TYPE_Set(b) (mdwFOTGPort(0x80) |= b)#define mdwOTGC_Control_A_SRP_RESP_TYPE_Clr() (mdwFOTGPort(0x80) &= (~BIT8))#define mdwOTGC_Control_VBUS_FLT_SEL_Rd() (mdwFOTGPort(0x80)& BIT10)#define mdwOTGC_Control_VBUS_FLT_SEL_Set() (mdwFOTGPort(0x80) |= BIT10)#define mdwOTGC_Control_VBUS_FLT_SEL_Clr() (mdwFOTGPort(0x80) &= (~BIT10))#define mdwOTGC_Control_B_SESS_END_Rd() (mdwFOTGPort(0x80)& BIT16)#define mdwOTGC_Control_B_SESS_VLD_Rd() (mdwFOTGPort(0x80)& BIT17)#define mdwOTGC_Control_A_SESS_VLD_Rd() (mdwFOTGPort(0x80)& BIT18)#define mdwOTGC_Control_A_VBUS_VLD_Rd() (mdwFOTGPort(0x80)& BIT19)#define mdwOTGC_Control_CROLE_Rd() (mdwFOTGPort(0x80)& BIT20) //0:Host 1:Peripheral#define mdwOTGC_Control_ID_Rd() (mdwFOTGPort(0x80)& BIT21) //0:A-Device 1:B-Device#define mdwOTGC_Control_Rd() (mdwFOTGPort(0x80))#define mdwOTGC_Control_Speed_Rd() ((mdwFOTGPort(0x80)& 0x00C00000)>>22)#define A_SRP_RESP_TYPE_VBUS 0x00#define A_SRP_RESP_TYPE_DATA_LINE 0x100//#define mwHost20_Control_ForceFullSpeed_Rd() (mdwFOTGPort(0x80) &= BIT12)//#define mwHost20_Control_ForceFullSpeed_Set() (mdwFOTGPort(0x80) |= BIT12)//#define mwHost20_Control_ForceFullSpeed_Clr() (mdwFOTGPort(0x80) &= ~BIT12)//#define mwHost20_Control_ForceHighSpeed_Rd() (mdwFOTGPort(0x80) &= BIT14)//#define mwHost20_Control_ForceHighSpeed_Set() (mdwFOTGPort(0x80) |= BIT14)//#define mwHost20_Control_ForceHighSpeed_Clr() (mdwFOTGPort(0x80) &= ~BIT14)#define mdwOTG20_Control_Phy_Reset_Set() (mdwFOTGPort(0x80)|=BIT15)#define mdwOTG20_Control_Phy_Reset_Clr() (mdwFOTGPort(0x80) &= ~BIT15)#define mdwOTG20_Control_OTG_Reset_Set() (mdwFOTGPort(0x80)|=BIT24)#define mdwOTG20_Control_OTG_Reset_Clr() (mdwFOTGPort(0x80) &= ~BIT24)//Offset:0x84(OTG Interrupt Status Register)#define mdwOTGC_INT_STS_Rd() (mdwFOTGPort(0x84))#define mdwOTGC_INT_STS_Clr(wValue) (mdwFOTGPort(0x84) |= wValue)#define OTGC_INT_BSRPDN BIT0#define OTGC_INT_ASRPDET BIT4#define OTGC_INT_AVBUSERR BIT5#define OTGC_INT_RLCHG BIT8#define OTGC_INT_IDCHG BIT9#define OTGC_INT_OVC BIT10#define OTGC_INT_BPLGRMV BIT11#define OTGC_INT_APLGRMV BIT12#define OTGC_INT_A_TYPE (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)#define OTGC_INT_B_TYPE (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)//Offset:0x088(OTG Interrupt Enable Register)#define mdwOTGC_INT_Enable_Rd() (mdwFOTGPort(0x88))#define mdwOTGC_INT_Enable_Set(wValue) (mdwFOTGPort(0x88)|= wValue)#define mdwOTGC_INT_Enable_Clr(wValue) (mdwFOTGPort(0x88)&= (~wValue))#define mdwOTGC_INT_Enable_BSRPDN_Set() (mdwFOTGPort(0x88) |= BIT0)#define mdwOTGC_INT_Enable_ASRPDET_Set() (mdwFOTGPort(0x88) |= BIT4)#define mdwOTGC_INT_Enable_AVBUSERR_Set() (mdwFOTGPort(0x88) |= BIT5)#define mdwOTGC_INT_Enable_RLCHG_Set() (mdwFOTGPort(0x88) |= BIT8)#define mdwOTGC_INT_Enable_IDCHG_Set() (mdwFOTGPort(0x88) |= BIT9)#define mdwOTGC_INT_Enable_OVC_Set() (mdwFOTGPort(0x88) |= BIT10)#define mdwOTGC_INT_Enable_BPLGRMV_Set() (mdwFOTGPort(0x88) |= BIT11)#define mdwOTGC_INT_Enable_APLGRMV_Set() (mdwFOTGPort(0x88) |= BIT12)#define mdwOTGC_INT_Enable_BSRPDN_Clr() (mdwFOTGPort(0x88) &= ~BIT0)#define mdwOTGC_INT_Enable_ASRPDET_Clr() (mdwFOTGPort(0x88) &= ~BIT4)#define mdwOTGC_INT_Enable_AVBUSERR_Clr() (mdwFOTGPort(0x88) &= ~BIT5)#define mdwOTGC_INT_Enable_RLCHG_Clr() (mdwFOTGPort(0x88) &= ~BIT8)#define mdwOTGC_INT_Enable_IDCHG_Clr() (mdwFOTGPort(0x88) &= ~BIT9)#define mdwOTGC_INT_Enable_OVC_Clr() (mdwFOTGPort(0x88) &= ~BIT10)#define mdwOTGC_INT_Enable_BPLGRMV_Clr() (mdwFOTGPort(0x88) &= ~BIT11)#define mdwOTGC_INT_Enable_APLGRMV_Clr() (mdwFOTGPort(0x88) &= ~BIT12)//Offset:0x0C0();;Interrupt Status bit#define mdwOTGC_GINT_STS_HOST_Rd() (mdwFOTGPort(0xC0) &= BIT2)#define mdwOTGC_GINT_STS_HOST_WClr() (mdwFOTGPort(0xC0) |= BIT2)#define mdwOTGC_GINT_STS_OTG_Rd() (mdwFOTGPort(0xC0) &= BIT1)#define mdwOTGC_GINT_STS_OTG_WClr() (mdwFOTGPort(0xC0) |= BIT1)#define mdwOTGC_GINT_STS_PERIPHERAL_Rd() (mdwFOTGPort(0xC0) &= BIT0)#define mdwOTGC_GINT_STS_PERIPHERAL_WClr() (mdwFOTGPort(0xC0) |= BIT0)//Offset:0x0C4();;Interrupt Mask bit#define mdwOTGC_GINT_HI_ACTIVE_Set() (mdwFOTGPort(0xC4) |= BIT3)#define mdwOTGC_GINT_HI_ACTIVE_Clr() (mdwFOTGPort(0xC4) &= ~BIT3)#define mdwOTGC_GINT_MASK_HOST_Set() (mdwFOTGPort(0xC4) |= BIT2)#define mdwOTGC_GINT_MASK_HOST_Clr() (mdwFOTGPort(0xC4) &= ~BIT2)#define mdwOTGC_GINT_MASK_OTG_Set() (mdwFOTGPort(0xC4) |= BIT1)#define mdwOTGC_GINT_MASK_OTG_Clr() (mdwFOTGPort(0xC4) &= ~BIT1)#define mdwOTGC_GINT_MASK_PERIPHERAL_Set() (mdwFOTGPort(0xC4) |= BIT0)#define mdwOTGC_GINT_MASK_PERIPHERAL_Clr() (mdwFOTGPort(0xC4) &= ~BIT0)//### For Peripheral #########################//Offset:0x100()#define mdwOTGC_ChipEnable_Set() (mdwFOTGPort(0x100)|=BIT5)#define mdwOTGC_HALFSPEEDEnable_Set() (mdwFOTGPort(0x100)|=BIT1))#define mdwOTGC_ChipEnable_INTEnable_Set() (mdwFOTGPort(0x100)|= (BIT5|BIT2)) //john0216 add//### For Host ##########################define mbHost20_USBCMD_RunStop_Rd() (mdwFOTGPort(0x10) &= BIT0)#define mbHost20_USBCMD_RunStop_Set() (mdwFOTGPort(0x10) |= BIT0)#define mbHost20_USBCMD_RunStop_Clr() (mdwFOTGPort(0x10) &= ~BIT0)#define mbHost20_USBCMD_AsynchronousEnable_Rd() (mdwFOTGPort(0x10) &= BIT5)#define mbHost20_USBCMD_AsynchronousEnable_Set() (mdwFOTGPort(0x10) |= BIT5)#define mbHost20_USBCMD_AsynchronousEnable_Clr() (mdwFOTGPort(0x10) &= ~BIT5)#define mbHost20_USBCMD_PeriodicEnable_Rd() (mdwFOTGPort(0x10) &= BIT4)#define mbHost20_USBCMD_PeriodicEnable_Set() (mdwFOTGPort(0x10) |= BIT4)#define mbHost20_USBCMD_PeriodicEnable_Clr() (mdwFOTGPort(0x10) &= ~BIT4)//For Host some interrupt#define mdwHost20_USBINTR_Rd() (mdwFOTGPort(0x18))#define mdwHost20_USBINTR_Set(dwValue) (mdwFOTGPort(0x18)=dwValue)#define mdwHost20_USBSTS_Rd() (mdwFOTGPort(0x14))#define mdwHost20_USBSTS_Set(dwValue) (mdwFOTGPort(0x14)=dwValue)#define mwHost20_PORTSC_ConnectStatus_Rd() (mdwFOTGPort(0x30)|=BIT0)//For Host Port Reset#define mwHost20_PORTSC_PortReset_Rd() (mdwFOTGPort(0x30) &= BIT8)#define mwHost20_PORTSC_PortReset_Set() (mdwFOTGPort(0x30) = BIT8)#define mwHost20_PORTSC_PortReset_Clr() (mdwFOTGPort(0x30) = 0)//For AP Command Definition#define OTG_AP_CMD_GET_STATE 1#define OTG_AP_CMD_SET_HOST 2#define OTG_AP_CMD_SET_IDLE 3#define OTG_AP_CMD_SET_PERIPHERAL 4#define OTG_AP_CMD_ENABLE_DEV 5 //john0217 add, enable device interrupt to let device begin to work#define OTG_AP_CMD_MDELAY_100 10#define OTG_AP_CMD_TEST_MDELAY 11#define OTG_AP_CMD_TEST_DUMP_REG 12#define OTG_AP_CMD_TEST_SET_REG_ADD 13#define OTG_AP_CMD_TEST_REG_WRITE 14//john0217 remove force speed//#define OTG_AP_CMD_TMP_FORCE_FULL 20//#define OTG_AP_CMD_TMP_FORCE_HIGH 21//#define OTG_AP_CMD_TMP_FORCE_CLEAN 22//--Function pre definestatic int OTGH_host_quick_Reset(void);void OTGP_Close(void);void OTGH_Close(void);void OTGP_Open(void);void OTGH_Open(void);void OTGC_A_PHY_Reset(void);int OTGC_Waiting_VBUS_On(u32 bmsec);int OTGC_Waiting_VBUS_Off(u32 bmsec);static void OTGC_enable_vbus_draw(u8 btype);void OTG_RoleChange(void);void OTGC_Init(void);static int OTGC_AP_ioctl(struct inode * inode, struct file * file,unsigned int cmd,unsigned long arg);int Host_Disconnect_for_OTG(struct usb_bus *bus, unsigned port_num);static int FOTG2XX_start_hnp(struct otg_transceiver *dev);⌨️ 快捷键说明
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