ehci-hcd-fusbh200.c

WiFi IP-Cam solution. FIC8120 platform VIA VT6656 USB Module driver source code.

/*
 * Copyright (c) 2000-2002 by David Brownell
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/smp_lock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <linux/interrupt.h>

//Add Einsn@VIA
#include <asm/proc/cache.h>//Faraday-EHCI(FUSBH200)

#ifdef CONFIG_USB_DEBUG
	#define DEBUG
#else
	#undef DEBUG
#endif

#include <linux/usb.h>

#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,32)
#include "../hcd.h"
#else
#include "../core/hcd.h"
#endif

//Add Einsn@VIA
#include "../FTC_Debug.h"//Faraday-EHCI(FUSBH200)

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/unaligned.h>


/*-------------------------------------------------------------------------*/

/*
 * EHCI hc_driver implementation ... experimental, incomplete.
 * Based on the final 1.0 register interface specification.
 *
 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
 * First was PCMCIA, like ISA; then CardBus, which is PCI.
 * Next comes "CardBay", using USB 2.0 signals.
 *
 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
 * Special thanks to Intel and VIA for providing host controllers to
 * test this driver on, and Cypress (including In-System Design) for
 * providing early devices for those host controllers to talk to!
 *
 * HISTORY:
 *
 * 2002-11-29	Correct handling for hw async_next register.
 * 2002-08-06	Handling for bulk and interrupt transfers is mostly shared;
 *	only scheduling is different, no arbitrary limitations.
 * 2002-07-25	Sanity check PCI reads, mostly for better cardbus support,
 * 	clean up HC run state handshaking.
 * 2002-05-24	Preliminary FS/LS interrupts, using scheduling shortcuts
 * 2002-05-11	Clear TT errors for FS/LS ctrl/bulk.  Fill in some other
 *	missing pieces:  enabling 64bit dma, handoff from BIOS/SMM.
 * 2002-05-07	Some error path cleanups to report better errors; wmb();
 *	use non-CVS version id; better iso bandwidth claim.
 * 2002-04-19	Control/bulk/interrupt submit no longer uses giveback() on
 *	errors in submit path.  Bugfixes to interrupt scheduling/processing.
 * 2002-03-05	Initial high-speed ISO support; reduce ITD memory; shift
 *	more checking to generic hcd framework (db).  Make it work with
 *	Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
 * 2002-01-14	Minor cleanup; version synch.
 * 2002-01-08	Fix roothub handoff of FS/LS to companion controllers.
 * 2002-01-04	Control/Bulk queuing behaves.
 *
 * 2001-12-12	Initial patch version for Linux 2.5.1 kernel.
 * 2001-June	Works with usb-storage and NEC EHCI on 2.4
 */
/*
#define DRIVER_VERSION "2003-Jan-22"
#define DRIVER_AUTHOR "David Brownell"
#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
*/
//Add Einsn@VIA
#define DRIVER_VERSION "2005-May-02"//Faraday-EHCI(FUSBH200)
#define DRIVER_AUTHOR "Faraday-SW"//Faraday-EHCI(FUSBH200)
#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver for Faraday FUSBH200"//Faraday-EHCI(FUSBH200)
//End Add

static const char	hcd_name [] = "ehci-hcd";


// #define EHCI_VERBOSE_DEBUG
// #define have_split_iso

#ifdef DEBUG
#define EHCI_STATS
#endif

#define INTR_AUTOMAGIC		/* urb lifecycle mode, gone in 2.5 */

/* magic numbers that can affect system performance */
#define	EHCI_TUNE_CERR		3	/* 0-3 qtd retries; 0 == don't stop */
#define	EHCI_TUNE_RL_HS		4	/* nak throttle; see 4.9 */
#define	EHCI_TUNE_RL_TT		0
#define	EHCI_TUNE_MULT_HS	1	/* 1-3 transactions/uframe; 4.10.3 */
#define	EHCI_TUNE_MULT_TT	1
#define	EHCI_TUNE_FLS		2	/* (small) 256 frame schedule */

#define EHCI_WATCHDOG_JIFFIES	(HZ/100)	/* arbitrary; ~10 msec */
#define EHCI_ASYNC_JIFFIES	(HZ/20)		/* async idle timeout */

/* Initial IRQ latency:  lower than default */
static int log2_irq_thresh = 0;		// 0 to 6
MODULE_PARM (log2_irq_thresh, "i");
MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");

#define	INTR_MASK (STS_IAA | STS_FATAL | STS_ERR | STS_INT)

/*-------------------------------------------------------------------------*/


//#include "ehci.h"
//Add Einsn@VIA
#include "ehci-FEHCI.h"//Faraday-EHCI(FOTG2XX)
#include "ehci-dbg.c"
//End Add

//Start;;Faraday-EHCI(FUSBH200)

//=============================================================================
// FEHCI_ReadSpeed()
// Description:
// Input:NA
// Output: int 0 => ok
//=============================================================================
static int FEHCI_ReadSpeed (void)//0=>None 1=>Full Speed 2=>High Speed
{
   int     base;//Bruce;;
   int     val;//Bruce;;         

   base=IO_ADDRESS((CPE_HOST20_BASE+0x40)); 
   val=readl(base);
    
   if (((val>>9)&0x03) == 2 )
   {
      base=IO_ADDRESS((CPE_HOST20_BASE+0x34)); 
      val=inl(base);
       
      val=val|0x0C;
      outl(val,base);  
      //Read again	
      val=inl(base);  
      return 2;
   }
   else if (((val>>9)&0x03) == 1 ) {
      return 1;
   }
   else {
      //Set EOF1 Time

      base=IO_ADDRESS((CPE_HOST20_BASE+0x34)); 
      val=inl(base);
       
      val=val|0x0C;
      outl(val,base);  
      //Read again	
      val=inl(base);
      return 0;             
   }
   return 0;
}

//=============================================================================
// FEHCI_ChipHalfSpeed()
// Description:
// Input:NA
// Output: int 0 => ok
//=============================================================================
static void FEHCI_ChipHalfSpeed (void)
{
   int     base;//Bruce;;
   int     val;//Bruce;;         

   base=IO_ADDRESS((CPE_HOST20_BASE+0x40)); //0x40 BIT2 
   val = inl(base);
   val|=(1<<2);//For HALFSPEEDEnable//For New-FUSBH200
   outl(val,base);  
}

//=============================================================================
// FEHCI_DriveVBUS()
// Description:
// Input:NA
// Output: int 0 => ok
//=============================================================================
static void FEHCI_DriveVBUS (void)
{
   int     base;//Bruce;;
   int     val;//Bruce;;         

   base=IO_ADDRESS((CPE_HOST20_BASE+0x40)); //0x40 BIT4
   val = inl(base);
   val&=~(1<<4);//Clear Bit4 to Turn on VBUS for new FUSBH200
   outl(val,base);       
}

//=============================================================================
// FEHCI_Interrupt_High_Active()
// Description:
// Input:NA
// Output: int 0 => ok
//=============================================================================
static void FEHCI_Interrupt_High_Active (int bActiveHigh)
{
   int base;//Bruce;;
   int val;//Bruce;; 
   
   base=IO_ADDRESS((CPE_HOST20_BASE+0x40)); //0x40 BIT3
   val = inl(base);
   if (bActiveHigh>0) {
      val|=(1<<3);//Set Bit3 for "Interrupt_OutPut_High_Set"
   }
   else {
	  val&=~(1<<3);//Clear Bit3 for "Interrupt_OutPut_Low_Set"
   }
   outl(val,base);  
}

//End;;Faraday-EHCI(FUSBH200)






/*-------------------------------------------------------------------------*/

/*
 * handshake - spin reading hc until handshake completes or fails
 * @ptr: address of hc register to be read
 * @mask: bits to look at in result of read
 * @done: value of those bits when handshake succeeds
 * @usec: timeout in microseconds
 *
 * Returns negative errno, or zero on success
 *
 * Success happens when the "mask" bits have the specified value (hardware
 * handshake done).  There are two failure modes:  "usec" have passed (major
 * hardware flakeout), or the register reads as all-ones (hardware removed).
 *
 * That last failure should_only happen in cases like physical cardbus eject
 * before driver shutdown. But it also seems to be caused by bugs in cardbus
 * bridge shutdown:  shutting down the bridge before the devices using it.
 */
static int handshake (u32 *ptr, u32 mask, u32 done, int usec)
{
	u32	result;

	do {
		result = readl (ptr);
		if (result == ~(u32)0)		/* card removed */
			return -ENODEV;
		result &= mask;
		if (result == done)
			return 0;
		udelay (1);
		usec--;
	} while (usec > 0);
	return -ETIMEDOUT;
}

/*
 * hc states include: unknown, halted, ready, running
 * transitional states are messy just now
 * trying to avoid "running" unless urbs are active
 * a "ready" hc can be finishing prefetched work
 */

/* force HC to halt state from unknown (EHCI spec section 2.3) */
static int ehci_halt (struct ehci_hcd *ehci)
{
	u32	temp = readl (&ehci->regs->status);

	if ((temp & STS_HALT) != 0)
		return 0;

	temp = readl (&ehci->regs->command);
	temp &= ~CMD_RUN;
	writel (temp, &ehci->regs->command);
	return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
}

/* reset a non-running (STS_HALT == 1) controller */
static int ehci_reset (struct ehci_hcd *ehci)
{
	u32	command = readl (&ehci->regs->command);

	command |= CMD_RESET;
	dbg_cmd (ehci, "reset", command);
	writel (command, &ehci->regs->command);
	ehci->hcd.state = USB_STATE_HALT;
	return handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
}

/* idle the controller (from running) */
static void ehci_ready (struct ehci_hcd *ehci)
{
	u32	temp;

#ifdef DEBUG
	if (!HCD_IS_RUNNING (ehci->hcd.state))
		BUG ();
#endif

	/* wait for any schedule enables/disables to take effect */
	temp = 0;
	if (ehci->async->qh_next.qh)
		temp = STS_ASS;
	if (ehci->next_uframe != -1)
		temp |= STS_PSS;
	if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
				temp, 16 * 125) != 0) {
		ehci->hcd.state = USB_STATE_HALT;
		return;
	}

	/* then disable anything that's still active */
	temp = readl (&ehci->regs->command);
	temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
	writel (temp, &ehci->regs->command);

	/* hardware can take 16 microframes to turn off ... */
	if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
				0, 16 * 125) != 0) {
		ehci->hcd.state = USB_STATE_HALT;
		return;
	}
	ehci->hcd.state = USB_STATE_READY;
}

/*-------------------------------------------------------------------------*/
/*
#include "ehci-hub.c"
#include "ehci-mem.c"
#include "ehci-q.c"
#include "ehci-sched.c"
*/
#include "ehci-hub-FEHCI.c"
#include "ehci-mem.c"
#include "ehci-q-FEHCI.c"
#include "ehci-sched-FEHCI.c"


//For Faraday FEHCI;;Start******************************************
static int ehci_FEHCI_Init (void)
{
 
 
        //For HALFSPEEDEnable
        FEHCI_ChipHalfSpeed();
  
        //Setting the Interrupt Low/High Active
          FEHCI_Interrupt_High_Active(1);
 
        //Turn on VBUS 
       FEHCI_DriveVBUS();
  
   return 0; 

}

//For Faraday FUSBH200;;End******************************************



/*-------------------------------------------------------------------------*/

static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);

static void ehci_watchdog (unsigned long param)
{
	struct ehci_hcd		*ehci = (struct ehci_hcd *) param;
	unsigned long		flags;

	spin_lock_irqsave (&ehci->lock, flags);

	/* lost IAA irqs wedge things badly; seen with a vt8235 */
	if (ehci->reclaim) {
		u32		status = readl (&ehci->regs->status);

		if (status & STS_IAA) {
			ehci_vdbg (ehci, "lost IAA\n");
			writel (STS_IAA, &ehci->regs->status);
			ehci->reclaim_ready = 1;
		}
	}

	ehci_work (ehci, NULL);
	if (ehci->reclaim && !timer_pending (&ehci->watchdog))
		mod_timer (&ehci->watchdog,
				jiffies + EHCI_WATCHDOG_JIFFIES);

 	/* stop async processing after it's idled a while */
	else if (ehci->async_idle) {
 		start_unlink_async (ehci, ehci->async);
 		ehci->async_idle = 0;
	}
	spin_unlock_irqrestore (&ehci->lock, flags);
}