_primary.vhd

来自「好用的UART通信源码」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity timer_top is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        sw1             : in     vl_logic;
        sw2             : in     vl_logic;
        led_seg         : out    vl_logic_vector(7 downto 0);
        led_sel         : out    vl_logic_vector(3 downto 0);
        led             : out    vl_logic
    );
end timer_top;