_primary.vhd

来自「好用的UART通信源码」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity pll_iobuf is
    port(
        i               : in     vl_logic;
        oe              : in     vl_logic;
        io              : inout  vl_logic;
        o               : out    vl_logic
    );
end pll_iobuf;