📄 rf.c
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/************************************************************************************
;copyright :shenzhen
;filename :rf.c
;RF :A7105
;rf crystal :16MHZ
;RF rate :250k
;control mcu :W78E52B
;writeby :dengyih
;describe :A7105 控制
;notice :Fdev 固定为 80k
;***********************************************************************
; --------------------
; P1.0 |1 40| VCC
; P1.1 |2 39| P0.0 ---- LCD_DATA0
; RF_SCK ---- P1.2 |3 38| P0.1 ---- LCD_DATA1
; RF_SDIO ---- P1.3 |4 37| P0.2 ---- LCD_DATA2
; P1.4 |5 36| P0.3 ---- LCD_DATA3
; RF_SCS ---- P1.5 |6 35| P0.4 ---- LCD_DATA4
; P1.6 |7 34| P0.5 ---- LCD_DATA5
; P1.7 |8 33| P0.6 ---- LCD_DATA6
; RST/Vpd |9 32| P0.7 ---- LCD_DATA7
; RXD/P3.0 |10 31| /EA/Vpp
; TXD/P3.1 |11 30| ALE/PROG
; RF_GPIO2 --- /INT0/P3.2 |12 29| /PSEN
; RF_GPIO1 --- /INT1/P3.3 |13 28| P2.7 ---- KEY4
; T0/P3.4 |14 27| P2.6 ---- KEY3
; RX\TX --- T1/P3.5 |15 26| P2.5 ---- KEY2
; /WR/P3.6 |16 25| P2.4 ---- KEY1
; /RD/P3.7 |17 24| P2.3
; XTAL2 |18 23| P2.2 ---- LCD_RW
; XTAL1 |19 22| P2.1 ---- LCD_RS
; VSS |20 21| P2.0 ---- LCD_EN
; --------------------
; W78E52B(PDIP)
;***********************************************************************/
#include "..\header\rf.h"
U8 const code Rf_Rate_Tab[7] = {19,9,7,4,3,1,0};
//25k,50k,62.5k,100k,125k,250k,500k
// A7105 寄存器默认配置
U8 const code A7105_Default_Par[51] =
{
//0x00 register
0x00, // RESET register : not use on config
//0x01 register
//#if(TEST_MODE)
// 0xc2, // direct mode
//#else
0x42, // MODE register: FIFO mode
//#endif
//0x02 register
0x00, // CALIBRATION register
//0x03 register
RF_FIFO_LEN - 1, // FIFO1 register : packet length
//0x04 register
0xc0, // FIFO2 register : FIFO pointer margin threshold 16/48bytes(TX/RX)
//0x05 register
0x00, // fifo register,not use on config
//0x06 register
0x00, // ID data register,not use on config
//0x07 register
0x00, // RCOSC1 register
0x00, // RCOSC2 register
0x00, // RCOSC3 register
//0x0a register
// 0x02, // CKO register,clk out enable,bit clock
0x00, // CKO disable
//0x0b register
0x01, // GPIO1 register :WTR output,enable GPIO1 output
0x09, // GPIO2 register :CD carrier detect,enable GPIO2 output
// GPIO1，2按上面设置时，在接收状态下GPIO2保持为低电平，GPIO1保持为高电平，
// 发送方发送一帧数据时，GPIO2会产生一个正脉冲，接收方GPIO2也会产生一个正脉冲
// 发送方发送一帧数据时，GPIO1会产生一个负脉冲，接收方GPIO2也会产生一个负脉冲
//0x0d register
0x05, // CLOCK register: Crystal oscillator enable bit
//0x0e register
0x01, // data rate select 250K
// data rate = system clock / 32*(SDR[7:0] + 1
// 0x04, // data rate = 100k
//0x0f register
0x14, // PLL register1, LO channel number select
// channel = 0x14 RF frequency = 2400MHZ + 500K * 20 = 2.410GHZ
//0x10 register
0x9e, // PLL register2,
// DBL = 1, crystal frequency double select
// RRC[1:0] = 00, Fpfd = Fcrystal(16MHZ) * (1 + DBL) /(RRC[1:0] + 1) = 32MHZ
// CHR[3:0] = 0x0F, channel frequency step setting
// channel setp frequency = 0.25 * Fpfd / (CHR[3:0] + 1) = 500KHZ
//0x11 register
0x4b, // PLL register3 BIP[7:0] = 75
0x00, // PLL register4 BFP[15:8] = 0
0x00, // PLL register5 BFP[7:0] = 0
//0x14 register
// 0x06, // TX register1
// frequency deviation power setting = [110]
// TX modulation disable
0x16, // enable tx modulation
//0x15 register
// 0x2b, // Fdev = 187k // TX register2
// Fpfd = 32MHZ,PDV[1:0] = 01,SDR[7:0] = 0000 0001
// Tx rate = Fpfd / (32 * (PDV[1:0]+1) * (SDR[7:0]+1)) = 250kbps
// TX frequency deviation = Fpfd * 127 * 2^FDP[2:0] * (FD[4:0]+1) /2^24 = 187.5KHZ
// 0x20, // Fdev = 15K @FD[2:0] = [110]
// 0x21, // Fdev = 31k @FD[2:0] = [110]
// 0x22, // Fdev = 46k @FD[2:0] = [110]
0x23, // Fdev = 62k @FD[2:0] = [110]
// 0x24, // Fdev = 80k @FD[2:0] = [110]
// 0x25, // Fdev = 93k @FD[2:0] = [110]
// 0x26, // Fdev = 108k @FD[2:0] = [110]
// 0x27, // Fdev = 124k @FD[2:0] = [110]
// 0x28, // Fdev = 139k @FD[2:0] = [110]
// 0x29, // Fdev = 155k @FD[2:0] = [110]
// 0x2a, // Fdev = 170k @FD[2:0] = [110]
// 0x2b, // Fdev = 186k @FD[2:0] = [110]
// 0x2c, // Fdev = 200k @FD[2:0] = [110]
// 0x2d, // Fdev = 217k @FD[2:0] = [110]
// 0x2e, // Fdev = 232k @FD[2:0] = [110]
// 0x2f, // Fdev = 248k @FD[2:0] = [110]
// 0x30, // Fdev = 263k @FD[2:0] = [110]
// 0x32, // Fdev = 294k @FD[2:0] = [110]
// 0x39, // Fdev = 400k @FD[2:0] = [110]
//0x16 register
0x12, // Delay register1
// DPR[2:0] = 0, TDL[1:0] = 2, PDL[2:0] = 2
// TX setting delay = 20*(TDL[1:0]+1)*(DPR[2:0]+1) = 20*3 = 60us
// PLL setting delay = 20*(PDL[2:0]+1)*(DPR[2:0]+1) = 20*3 = 60us
//0x17 register
0xf8, // Delay register2
// Crystal turn on delay 2.5ms
// AGC delay 40us
// RSSI measurement delay 10us
//0x18 register
0x26, // RX register
// Demodulator filter bandwidth = 1M
// Demodulator gain select * 3
// BPF bandwidth 500khz
// Up side band select
// 0x36, // AFC = 1,frequency compensation select (auto)
//0x19 register
0x80, // RX gain register1, 手动校验VGA, PGA gain 12db,mixer gain 24db, LNA gain 24db
//0x1a register
0x80, // RX gain register2, VGA calibrate upper limit target
//0x1b register
0x00, // RX gain register3, VGA calibrate lower limit target
//0x1c register
0x0e, // RX gain register4, VGC calibrate continues until ID code word is received
// Mixer current select 1.2mA
// LNA current select 2.0mA
//0x1d register
0x32, // RSSI register RSSI 50
//0x1e register
0xc3, // ADC register
//0x1f register
// 0x0f, // CODE register1, ID length 4 bytes, preamble length 4 bytes
// 0x4f, // open manchester
0x5f, // open manchester, FEC
//0x20 register
0x12, // CODE register2,
//0x21 register
0x00, // CODE register3,
//0x22 register
0x00, // IF calibration1, auto calibration IF
//0x23 register
0x00, // IF calibration2, read only
//0x24 register
0x00, // VCO current calibration register
//0x25 register
0x00, // VCO Single band calibration register1
// auto calibration
//0x26 register
0x3a, // VCO Single band calibration register2
// REGA = 1.1V,VCO tuning voltage =0.3V
//0x27 register
0x00, // battery register default
//0x28 register
0x17, // TX test register default
//0x29 register
0x47, // RX DEM test registe1 default
//0x2a register
0x80, // RX DEM test register2 defalut
//0x2b register
0x01, // charge pump current register
// charge pump curretn = 1.0mA
//0x2c register
0x05, // Crystal test register default
//0x2d register
0x45, // PLL TEST register default
//0x2e register
0x18, // VCO test register1 default
//0x2f register
0x00, // VCO test register2 default
//0x30 register
0x01, // IFAT register default
//0x31 register
0x0f, // RScale register RSSI tuning scale default
//0x32 register
0x00 // Filter test register default
};
/****************************************************************
name: ini rf
input: none
output: none
describe: 初始化A7105
notice:
creat date: 2008-7-20
creator: dengyihong
****************************************************************/
void ini_rf(void)
{
set_rf_io();
A7105_reset_chip();
delay_2us(50000);
delay_2us(50000);
A7105_write_ID();
A7105_config_chip();
A7105_calibration();
if(System_Mode)
{
A7105_setup_channel(Rf_Rec_Channel);
A7105_setup_wpll();
A7105_entry_tx();
}
else
{
A7105_setup_channel(Rf_Rec_Channel);
A7105_setup_wpll();
delay_2us(100);
A7105_entry_rx(); // 接收状态
}
}
/****************************************************************
name: A7105_config_chip
input: none
output: none
describe: 配置A7105
notice:
creat date: 2008-7-20
creator: dengyihong
****************************************************************/
void A7105_config_chip(void)
{
U8 i = 0;
// 0x00 mode register, for reset
// 0x05 fifo data register
// 0x06 id code register
// 0x23 IF calibration II, only read
// 0x32 filter test register
if(System_Mode)
{
A7105_write_register(1,0xc2); // direct mode
for(i=0x02; i<=0x04; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
/*
for(i=0x07; i<=0x13; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
*/
for(i=0x07; i<0x0e; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
A7105_write_register(0x0e,Rf_Rate_Tab[Rf_Rate_Cnt]); // set data rate
for(i=0x0f; i<=0x13; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
A7105_write_register(0x14,0x06); // close TX modulation
for(i=0x15; i<=0x22; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
}
else
{
for(i=0x01; i<=0x04; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
for(i=0x07; i<0x0e; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
A7105_write_register(0x0e,Rf_Rate_Tab[Rf_Rate_Cnt]); // set data rate
for(i=0x0f; i<=0x22; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
/*
for(i=0x07; i<=0x22; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
*/
}
for (i=0x24; i<=0x31; i++)
{
A7105_write_register(i,A7105_Default_Par[i]);
}
}
/****************************************************************
name: set_rf_io
input: none
output: none
describe: 上电时设置RF的I/O口方向及状态
notice:
creat date: 2008-7-20
creator: dengyihong
****************************************************************/
void set_rf_io(void)
{
RF_SCK_LOW();
RF_SDIO_LOW();
RF_SCS_HIGH();
RF_TX_PA_OFF();
RF_GPIO1_INPUT();
}
/*******************************************************
name: A7105_calibration
input: none
output:
describe: 校验A7105
notice: 1. RF 上电后一定要调用该程序对VCO进行校验
2. 校验时需在 stby 状态
creat date: 2008-7-20
creator: dengyihong
********************************************************/
void A7105_calibration(void)
{
U8 temp = 0;
// standby状态下校准IF
A7105_entry_stby();
A7105_write_register(RF_REG_CALIBRATION,0x01);
do
{
temp = A7105_read_register(RF_REG_CALIBRATION);
temp &= 0x01;
}while(temp);
temp = A7105_read_register(RF_REG_IF_CALIBRATION1);
temp &= 0x10;
if(temp)
{
// 校准出错
}
// anual vco current band 3,vco band 1
A7105_write_register(RF_REG_VCO_CURRENT_CAL,0x13);
A7105_write_register(RF_REG_VCO_BAND_CAL1,0x09);
A7105_entry_stby();
}
/***************************************************
name: A7105_entry_stby
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