📄 rf.lst
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C51 COMPILER V7.06 RF 10/29/2008 11:22:42 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE RF
OBJECT MODULE PLACED IN rf.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE source\rf.c ROM(COMPACT) BROWSE DEBUG OBJECTEXTEND PRINT(.\rf.lst) OBJECT(r
-f.obj)
stmt level source
1 /************************************************************************************
2 ;copyright :shenzhen coolwaveasia
3 ;filename :rf.c
4 ;RF :A7105
5 ;rf crystal :16MHZ
6 ;RF rate :250k
7 ;control mcu :W78E52B
8 ;writeby :dengyihong
9 ;describe :A7105 控制
10 ;notice :Fdev 固定为 80k
11 ;***********************************************************************
12 ; --------------------
13 ; P1.0 |1 40| VCC
14 ; P1.1 |2 39| P0.0 ---- LCD_DATA0
15 ; RF_SCK ---- P1.2 |3 38| P0.1 ---- LCD_DATA1
16 ; RF_SDIO ---- P1.3 |4 37| P0.2 ---- LCD_DATA2
17 ; P1.4 |5 36| P0.3 ---- LCD_DATA3
18 ; RF_SCS ---- P1.5 |6 35| P0.4 ---- LCD_DATA4
19 ; P1.6 |7 34| P0.5 ---- LCD_DATA5
20 ; P1.7 |8 33| P0.6 ---- LCD_DATA6
21 ; RST/Vpd |9 32| P0.7 ---- LCD_DATA7
22 ; RXD/P3.0 |10 31| /EA/Vpp
23 ; TXD/P3.1 |11 30| ALE/PROG
24 ; RF_GPIO2 --- /INT0/P3.2 |12 29| /PSEN
25 ; RF_GPIO1 --- /INT1/P3.3 |13 28| P2.7 ---- KEY4
26 ; T0/P3.4 |14 27| P2.6 ---- KEY3
27 ; RX\TX --- T1/P3.5 |15 26| P2.5 ---- KEY2
28 ; /WR/P3.6 |16 25| P2.4 ---- KEY1
29 ; /RD/P3.7 |17 24| P2.3
30 ; XTAL2 |18 23| P2.2 ---- LCD_RW
31 ; XTAL1 |19 22| P2.1 ---- LCD_RS
32 ; VSS |20 21| P2.0 ---- LCD_EN
33 ; --------------------
34 ; W78E52B(PDIP)
35 ;***********************************************************************/
36
37 #include "..\header\rf.h"
38
39 U8 const code Rf_Rate_Tab[7] = {19,9,7,4,3,1,0};
40 //25k,50k,62.5k,100k,125k,250k,500k
41
42
43 // A7105 寄存器默认配置
44 U8 const code A7105_Default_Par[51] =
45 {
46 //0x00 register
47 0x00, // RESET register : not use on config
48
49 //0x01 register
50 //#if(TEST_MODE)
51 // 0xc2, // direct mode
52 //#else
53 0x42, // MODE register: FIFO mode
54 //#endif
C51 COMPILER V7.06 RF 10/29/2008 11:22:42 PAGE 2
55
56 //0x02 register
57 0x00, // CALIBRATION register
58
59 //0x03 register
60 RF_FIFO_LEN - 1, // FIFO1 register : packet length
61
62 //0x04 register
63 0xc0, // FIFO2 register : FIFO pointer margin threshold 16/48bytes(TX/RX)
64
65 //0x05 register
66 0x00, // fifo register,not use on config
67
68 //0x06 register
69 0x00, // ID data register,not use on config
70
71 //0x07 register
72 0x00, // RCOSC1 register
73 0x00, // RCOSC2 register
74 0x00, // RCOSC3 register
75
76 //0x0a register
77 // 0x02, // CKO register,clk out enable,bit clock
78 0x00, // CKO disable
79
80 //0x0b register
81 0x01, // GPIO1 register :WTR output,enable GPIO1 output
82 0x09, // GPIO2 register :CD carrier detect,enable GPIO2 output
83 // GPIO1，2按上面设置时，在接收状态下GPIO2保持为低电平，GPIO1保持为高电平，
84 // 发送方发送一帧数据时，GPIO2会产生一个正脉冲，接收方GPIO2也会产生一个正脉冲
85 // 发送方发送一帧数据时，GPIO1会产生一个负脉冲，接收方GPIO2也会产生一个负脉冲
86 //0x0d register
87 0x05, // CLOCK register: Crystal oscillator enable bit
88
89 //0x0e register
90 0x01, // data rate select 250K
91 // data rate = system clock / 32*(SDR[7:0] + 1
92 // 0x04, // data rate = 100k
93
94 //0x0f register
95 0x14, // PLL register1, LO channel number select
96 // channel = 0x14 RF frequency = 2400MHZ + 500K * 20 = 2.410GHZ
97
98 //0x10 register
99 0x9e, // PLL register2,
100 // DBL = 1, crystal frequency double select
101 // RRC[1:0] = 00, Fpfd = Fcrystal(16MHZ) * (1 + DBL) /(RRC[1:0] + 1) = 32MHZ
102 // CHR[3:0] = 0x0F, channel frequency step setting
103 // channel setp frequency = 0.25 * Fpfd / (CHR[3:0] + 1) = 500KHZ
104
105 //0x11 register
106 0x4b, // PLL register3 BIP[7:0] = 75
107 0x00, // PLL register4 BFP[15:8] = 0
108 0x00, // PLL register5 BFP[7:0] = 0
109
110 //0x14 register
111 // 0x06, // TX register1
112 // frequency deviation power setting = [110]
113 // TX modulation disable
114 0x16, // enable tx modulation
115
116 //0x15 register
C51 COMPILER V7.06 RF 10/29/2008 11:22:42 PAGE 3
117 // 0x2b, // Fdev = 187k // TX register2
118 // Fpfd = 32MHZ,PDV[1:0] = 01,SDR[7:0] = 0000 0001
119 // Tx rate = Fpfd / (32 * (PDV[1:0]+1) * (SDR[7:0]+1)) = 250kbps
120 // TX frequency deviation = Fpfd * 127 * 2^FDP[2:0] * (FD[4:0]+1) /2^24 = 187.5K
-HZ
121
122 // 0x20, // Fdev = 15K @FD[2:0] = [110]
123 // 0x21, // Fdev = 31k @FD[2:0] = [110]
124 // 0x22, // Fdev = 46k @FD[2:0] = [110]
125 0x23, // Fdev = 62k @FD[2:0] = [110]
126 // 0x24, // Fdev = 80k @FD[2:0] = [110]
127 // 0x25, // Fdev = 93k @FD[2:0] = [110]
128 // 0x26, // Fdev = 108k @FD[2:0] = [110]
129 // 0x27, // Fdev = 124k @FD[2:0] = [110]
130 // 0x28, // Fdev = 139k @FD[2:0] = [110]
131 // 0x29, // Fdev = 155k @FD[2:0] = [110]
132 // 0x2a, // Fdev = 170k @FD[2:0] = [110]
133 // 0x2b, // Fdev = 186k @FD[2:0] = [110]
134 // 0x2c, // Fdev = 200k @FD[2:0] = [110]
135 // 0x2d, // Fdev = 217k @FD[2:0] = [110]
136 // 0x2e, // Fdev = 232k @FD[2:0] = [110]
137 // 0x2f, // Fdev = 248k @FD[2:0] = [110]
138 // 0x30, // Fdev = 263k @FD[2:0] = [110]
139 // 0x32, // Fdev = 294k @FD[2:0] = [110]
140 // 0x39, // Fdev = 400k @FD[2:0] = [110]
141
142 //0x16 register
143 0x12, // Delay register1
144 // DPR[2:0] = 0, TDL[1:0] = 2, PDL[2:0] = 2
145 // TX setting delay = 20*(TDL[1:0]+1)*(DPR[2:0]+1) = 20*3 = 60us
146 // PLL setting delay = 20*(PDL[2:0]+1)*(DPR[2:0]+1) = 20*3 = 60us
147
148 //0x17 register
149 0xf8, // Delay register2
150 // Crystal turn on delay 2.5ms
151 // AGC delay 40us
152 // RSSI measurement delay 10us
153
154 //0x18 register
155 0x26, // RX register
156 // Demodulator filter bandwidth = 1M
157 // Demodulator gain select * 3
158 // BPF bandwidth 500khz
159 // Up side band select
160 // 0x36, // AFC = 1,frequency compensation select (auto)
161
162 //0x19 register
163 0x80, // RX gain register1, 手动校验VGA, PGA gain 12db,mixer gain 24db, LNA gain 24db
-
164
165 //0x1a register
166 0x80, // RX gain register2, VGA calibrate upper limit target
167
168 //0x1b register
169 0x00, // RX gain register3, VGA calibrate lower limit target
170
171 //0x1c register
172 0x0e, // RX gain register4, VGC calibrate continues until ID code word is received
173 // Mixer current select 1.2mA
174 // LNA current select 2.0mA
175
176 //0x1d register
C51 COMPILER V7.06 RF 10/29/2008 11:22:42 PAGE 4
177 0x32, // RSSI register RSSI 50
178
179 //0x1e register
180 0xc3, // ADC register
181
182 //0x1f register
183 // 0x0f, // CODE register1, ID length 4 bytes, preamble length 4 bytes
184 // 0x4f, // open manchester
185 0x5f, // open manchester, FEC
186
187 //0x20 register
188 0x12, // CODE register2,
189
190 //0x21 register
191 0x00, // CODE register3,
192
193 //0x22 register
194 0x00, // IF calibration1, auto calibration IF
195
196 //0x23 register
197 0x00, // IF calibration2, read only
198
199 //0x24 register
200 0x00, // VCO current calibration register
201
202 //0x25 register
203 0x00, // VCO Single band calibration register1
204 // auto calibration
205
206 //0x26 register
207 0x3a, // VCO Single band calibration register2
208 // REGA = 1.1V,VCO tuning voltage =0.3V
209
210 //0x27 register
211 0x00, // battery register default
212
213 //0x28 register
214 0x17, // TX test register default
215
216 //0x29 register
217 0x47, // RX DEM test registe1 default
218
219 //0x2a register
220 0x80, // RX DEM test register2 defalut
221
222 //0x2b register
223 0x01, // charge pump current register
224 // charge pump curretn = 1.0mA
225
226 //0x2c register
227 0x05, // Crystal test register default
228
229 //0x2d register
230 0x45, // PLL TEST register default
231
232 //0x2e register
233 0x18, // VCO test register1 default
234
235 //0x2f register
236 0x00, // VCO test register2 default
237
238 //0x30 register
C51 COMPILER V7.06 RF 10/29/2008 11:22:42 PAGE 5
239 0x01, // IFAT register default
240
241 //0x31 register
242 0x0f, // RScale register RSSI tuning scale default
243
244 //0x32 register
245 0x00 // Filter test register default
246 };
247
248
249 /****************************************************************
250 name: ini rf
251 input: none
252 output: none
253 describe: 初始化A7105
254 notice:
255 creat date: 2008-7-20
256 creator: dengyihong
257 ****************************************************************/
258 void ini_rf(void)
259 {
260 1 set_rf_io();
261 1 A7105_reset_chip();
262 1 delay_2us(50000);
263 1 delay_2us(50000);
264 1
265 1 A7105_write_ID();
266 1
267 1 A7105_config_chip();
268 1
269 1 A7105_calibration();
270 1
271 1 if(System_Mode)
272 1 {
273 2 A7105_setup_channel(Rf_Rec_Channel);
274 2 A7105_setup_wpll();
275 2 A7105_entry_tx();
276 2 }
277 1 else
278 1 {
279 2 A7105_setup_channel(Rf_Rec_Channel);
280 2 A7105_setup_wpll();
281 2 delay_2us(100);
282 2 A7105_entry_rx(); // 接收状态
283 2 }
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