75x_mrcc.c

嵌入式实验源码。包括：电源管理、复位、时钟管理

/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name          : 75x_mrcc.c
* Author             : MCD Application Team
* Date First Issued  : 03/10/2006
* Description        : This file provides all the MRCC software functions.
********************************************************************************
* History:
* 03/10/2006 : V0.1
* mm/dd/yyyy
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/* Includes ------------------------------------------------------------------*/
#include "75x_mrcc.h"

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MRCC_FLAG_Mask    0x1F    /* MRCC Flag Mask */

/* MRCC_PWRCTRL mask bits */
#define MRCC_LP_Set_Mask             0x00000001
#define MRCC_LP_Reset_Mask           0xFFFFFFFE
#define MRCC_SWRESET_Mask            0x00000002
#define MRCC_WFI_Mask                0x00000004
#define MRCC_STANDBY_Mask            0x00000006
#define MRCC_LPMC_Reset_Mask         0xFFFFFFF9
#define MRCC_LPDONE_Reset_Mask       0xFFFFFF7F
#define MRCC_LPPARAM_Reset_Mask      0xFFFF1FFF
#define MRCC_WFIParam_Reset_Mask     0xFFFF1FEF
#define MRCC_CKRTCSEL_Set_Mask       0x03000000
#define MRCC_CKRTCSEL_Reset_Mask     0xFCFFFFFF
#define MRCC_CKRTCOK_Mask            0x08000000
#define MRCC_LPOSCEN_Mask            0x10000000
#define MRCC_OSC32KEN_Mask           0x20000000
            
/* MRCC_CLKCTL mask bits */
#define MRCC_PPRESC_Set_Mask        0x00000003
#define MRCC_PPRESC_Reset_Mask      0xFFFFFFFC
#define MRCC_PPRESC2_Mask           0x00000004
#define MRCC_HPRESC_Set_Mask        0x00000018
#define MRCC_HPRESC_Reset_Mask      0xFFFFFFE7
#define MRCC_MCOS_Reset_Mask        0xFFFFFF3F
#define MRCC_DIV2_Set_Mask          0x00008000
#define MRCC_DIV2_Reset_Mask        0xFFFF7FFF
#define MRCC_OSC4MBYP_Set_Mask      0x00010000
#define MRCC_OSC4MBYP_Reset_Mask    0xFFFEFFFF
#define MRCC_OSC4MOFF_Set_Mask      0x00020000  
#define MRCC_OSC4MOFF_Reset_Mask    0xFFFDFFFF
#define MRCC_NCKDF_Set_Mask         0x00040000
#define MRCC_NCKDF_Reset_Mask       0xFFFBFFFF
#define MRCC_CKOSCSEL_Set_Mask      0x00200000
#define MRCC_CKOSCSEL_Reset_Mask    0xFFDFFFFF
#define MRCC_CKUSBSEL_Mask          0x00400000
#define MRCC_CKSEL_Set_Mask         0x00800000
#define MRCC_CKSEL_Reset_Mask       0xFF7FFFFF
#define MRCC_CKSEL_CKOSCSEL_Mask    0x00A00000
#define MRCC_PLLEN_Set_Mask         0x01000000
#define MRCC_PLLEN_Reset_Mask       0xFEFFFFFF
#define MRCC_PLL2EN_Set_Mask        0x02000000
#define MRCC_PLL2EN_Reset_Mask      0xFDFFFFFF
#define MRCC_MX_Set_Mask            0x18000000
#define MRCC_MX_Reset_Mask          0xE7FFFFFF
#define MRCC_LOCK_Mask              0x80000000
#define MRCC_PLLEN_LOCK_Mask        0x81000000

/* MRCC_RFSR mask bits */
#define MRCC_BCOUNTM_Reset_Mask    0xFF00FFFF

/* Typical Value of the OSC4M in Hz */
#define OSC4M_Value    4000000   

/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */
#define OSC4M_Div128_Value    31250
   
/* Typical Value of the OS32K Oscillator Frequency in Hz */
#define OSC32K_Value    32768     

/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */
#define LPOSC_Value    245000   

/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */
#define FREEOSC_Value    5000000 

/* Time out for OSC4M start up */
#define OSC4MStartUp_TimeOut   0xFE

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static ErrorStatus SetCKSYS_FREEOSC(void);
static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State);
static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul);
static ErrorStatus SetCKSYS_RTC(u32 PLL_State);
static void WriteLPBit(void);
static void WriteCKOSCSELBit(void);

/* Private functions ---------------------------------------------------------*/

/*******************************************************************************
* Function Name  : MRCC_DeInit
* Description    : Deinitializes the MRCC peripheral registers to their default
*                  reset values. The MRCC_PWRCTRL register is not reset by this 
*                  function.
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
void MRCC_DeInit(void)
{
  /* Reset CKSEL bit */
  MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;
  
  if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)
  { 
    /* Clear CKOSCSEL bit ----------------------------------------------------*/
    /* Execute CKOSCSEL bit writing sequence */
    WriteCKOSCSELBit();
  }
    
  /* Disable PLL */
  MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; 
  
  /* Reset OSC4MOFF and OSC4MBYP bits */
  MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask;
  
  /* Clear NCKDF bit */
  MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask;

  /* Set CKSEL bit */
  MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask;
  
  /* Reset CLKCTL register bits except CKSEL one */
  MRCC->CLKCTL &= 0x80800000;
  
  /* Reset CKSEL bit */
  MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask;

  /* Set BCOUNTM bits to theire reset value */
  MRCC->RFSR |= 0x00FF0000;
   
  /* Reset PCLKEN register bits */
  MRCC->PCLKEN = 0x00;
  
  /* Reset PSWRES register bits */
  MRCC->PSWRES = 0x00;

  /* Clear NCKDF bit */
  MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask;
}

/*******************************************************************************
* Function Name  : MRCC_CKSYSConfig
* Description    : Configures the system clock (CK_SYS).
* Input          : - MRCC_CKSYS: specifies the clock source used as system clock.
*                    This parameter can be one of the following values:
*                          - MRCC_CKSYS_FREEOSC
*                          - MRCC_CKSYS_OSC4M
*                          - MRCC_CKSYS_OSC4MPLL
*                          - MRCC_CKSYS_RTC (RTC clock source must be previously
*                            configured using MRCC_CKRTCConfig() function)
*                : - MRCC_PLL: specifies the PLL configuration.
*                    This parameter can be one of the following values:
*                          - MRCC_PLL_Disabled: PLL disabled
*                          - MRCC_PLL_NoChange: No change on PLL configuration
*                          - MRCC_PLL_Mul_12: Multiplication by 12
*                          - MRCC_PLL_Mul_14: Multiplication by 14
*                          - MRCC_PLL_Mul_15: Multiplication by 15
*                          - MRCC_PLL_Mul_16: Multiplication by 16
* Output         : None
* Return         : An ErrorStatus enumuration value:
*                         - SUCCESS: Clock configuration succeeded
*                         - ERROR: Clock configuration failed
*******************************************************************************/
ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL)
{
  ErrorStatus Status = ERROR;

  switch(MRCC_CKSYS)
  {
    case MRCC_CKSYS_FREEOSC:
      if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))
      {
        Status = SetCKSYS_FREEOSC();
      }
      break;

    case MRCC_CKSYS_OSC4M:
      if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange))
      {
        Status = SetCKSYS_OSC4M(MRCC_PLL);
      }
      break;

    case MRCC_CKSYS_OSC4MPLL:
      if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) ||
         (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16))
      {
        Status = SetCKSYS_OSC4MPLL(MRCC_PLL);
      }
      break;