📄 75x_pwm.c
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PWM->OMR1 &= PWM_OC1C_Mask;
PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set;
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
/* Sets the OC1 wave polarity */
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
{
PWM->OMR1 |= PWM_OC1P_Set;
}
else
{
PWM->OMR1 &= PWM_OC1P_Reset;
}
/* Sets the OC1N wave polarity */
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
{
PWM->OMR1 |= PWM_OC1NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC1NP_Reset;
}
}/* End complementary case */
/* Single PWM Output configuratuion */
else
{
switch(PWM_InitStruct->PWM_OCState)
{
case PWM_OCState_Enable:
{
/* Configures Channel 1 on Output Compare mode */
PWM->OMR1 &= PWM_OC1C_Mask;
PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable;
PWM->OMR1 |= PWM_PLD1_Set;
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
/* Sets the OC1 wave polarity */
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
{
PWM->OMR1 |= PWM_OC1P_Set;
}
else
{
PWM->OMR1 &= PWM_OC1P_Reset;
}
}
break;
case PWM_OCState_Disable:
{
/* OC1E = 0 and OSSR = 0 sets the polarity */
PWM->OMR1 &= PWM_OC1_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCState_OffState:
{
/* OC1E = 0 and OSSR = 1 and sets the polarity */
PWM->OMR1 &= PWM_OC1_Disable;
DTR_REG |= PWM_OSSR_Set;
/* Sets the OC1 wave polarity */
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
{
PWM->OMR1 |= PWM_OC1P_Set;
}
else
{
PWM->OMR1 &= PWM_OC1P_Reset;
}
}
break;
}
switch(PWM_InitStruct->PWM_OCNState)
{
case PWM_OCNState_Enable:
{
/* Configures Channel 1N on Output Compare mode */
PWM->OMR1 &= PWM_OC1C_Mask;
PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set;
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
/* Sets the OC1N wave polarity */
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
{
PWM->OMR1 |= PWM_OC1NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC1NP_Reset;
}
}
break;
case PWM_OCNState_Disable:
{
/* OC1N = 0 OSSR = 0 */
PWM->OMR1 &= PWM_OC1N_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCNState_OffState:
{
/* OC1N = 0 OSSR = 1 and sets the polarity */
PWM->OMR1 &= PWM_OC1N_Disable;
DTR_REG |= PWM_OSSR_Set;
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
{
PWM->OMR1 |= PWM_OC1NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC1NP_Reset;
}
}
break;
}
} /* End not complementary case */
}/* end channel 1 */
/*Channel 2 Configuration-----------------------------------------------------*/
if(PWM_InitStruct->PWM_Channel == PWM_Channel_2)
{
/* PWM Output Complementary Configuration */
if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)
{
/* Configures Channel 2 on Output Compare mode */
PWM->OMR1 &= PWM_OC2C_Mask;
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set;
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
/* Set the OC2 wave polarity */
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
{
PWM->OMR1 |= PWM_OC2P_Set;
}
else
{
PWM->OMR1 &= PWM_OC2P_Reset;
}
/* Sets the OC2N wave polarity */
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
{
PWM->OMR1 |= PWM_OC2NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC2NP_Reset;
}
}/* End complentary case */
else
/* Single PWM Output configuratuion */
{
switch(PWM_InitStruct->PWM_OCState)
{
case PWM_OCState_Enable:
{
/* Configures Channel 2 on Output Compare mode */
PWM->OMR1 &= PWM_OC2C_Mask;
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set;
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
/* Sets the OC2 wave polarity */
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
{
PWM->OMR1 |= PWM_OC2P_Set;
}
else
{
PWM->OMR1 &= PWM_OC2P_Reset;
}
}
break;
case PWM_OCState_Disable:
{
/* OC2E = 0 and OSSR = 0 */
PWM->OMR1 &= PWM_OC2_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCState_OffState:
{
/* OC2E = 0 and OSSR = 1 sets the polarity */
PWM->OMR1 &= PWM_OC2_Disable;
DTR_REG |= PWM_OSSR_Set;
/* Sets the OC2 wave polarity */
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
{
PWM->OMR1 |= PWM_OC2P_Set;
}
else
{
PWM->OMR1 &= PWM_OC2P_Reset;
}
}
break;
}
switch(PWM_InitStruct->PWM_OCNState)
{
case PWM_OCNState_Enable:
{
/* Configures Channel 2N on Output Compare mode */
PWM->OMR1 &= PWM_OC2C_Mask;
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set;
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
/* Sets the OC2 wave polarity */
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
{
PWM->OMR1 |= PWM_OC2NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC2NP_Reset;
}
}
break;
case PWM_OCNState_Disable:
{
/* OC2N = 0 OSSR = 0 */
PWM->OMR1 &= PWM_OC2N_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCNState_OffState:
{
/* OC2N = 0 OSSR = 1 and sets the polarity */
PWM->OMR1 &= PWM_OC2N_Disable;
DTR_REG |= PWM_OSSR_Set;
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
{
PWM->OMR1 |= PWM_OC2NP_Set;
}
else
{
PWM->OMR1 &= PWM_OC2NP_Reset;
}
}
break;
}
} /* End not complementary case */
}/* end channel 2 */
/*Channel 3 Configuration-----------------------------------------------------*/
if(PWM_InitStruct->PWM_Channel == PWM_Channel_3)
{
/* PWM Output Complementary Configuration */
if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)
{
/* Configures Channel 3 on Output Compare mode */
PWM->OMR2 &= PWM_OC3C_Mask;
PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set;
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
/* Sets the OC3 wave polarity */
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
{
PWM->OMR2 |= PWM_OC3P_Set;
}
else
{
PWM->OMR2 &= PWM_OC3P_Reset;
}
/* Sets the OC3N wave polarity */
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
{
PWM->OMR2 |= PWM_OC3NP_Set;
}
else
{
PWM->OMR2 &= PWM_OC3NP_Reset;
}
}/* End complementary case */
else
/* Single PWM Output configuratuion */
{
switch(PWM_InitStruct->PWM_OCState)
{
case PWM_OCState_Enable:
{
/* Configures Channel 3 on Output Compare mode */
PWM->OMR2 &= PWM_OC3C_Mask;
PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set;
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
/* Sets the OCC wave polarity */
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
{
PWM->OMR2 |= PWM_OC3P_Set;
}
else
{
PWM->OMR2 &= PWM_OC3P_Reset;
}
}
break;
case PWM_OCState_Disable:
{
/* OC3E = 0 and OSSR = 0 */
PWM->OMR2 &= PWM_OC3_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCState_OffState:
{
/* OC3E = 0 and OSSR = 1 sets the polarity */
PWM->OMR2 &= PWM_OC3_Disable;
DTR_REG |= PWM_OSSR_Set;
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
{
PWM->OMR2 |= PWM_OC3P_Set;
}
else
{
PWM->OMR2 &= PWM_OC3P_Reset;
}
}
break;
}
switch(PWM_InitStruct->PWM_OCNState)
{
case PWM_OCNState_Enable:
{
/* Configures Channel 3N on Output Compare mode */
PWM->OMR2 &= PWM_OC3C_Mask;
PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set;
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
/* Sets the OC3 wave polarity */
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
{
PWM->OMR2 |= PWM_OC3NP_Set;
}
else
{
PWM->OMR2 &= PWM_OC3NP_Reset;
}
}
break;
case PWM_OCNState_Disable:
{
/* OC3N = 0 OSSR = 0 */
PWM->OMR2 &= PWM_OC3N_Disable;
DTR_REG &= PWM_OSSR_Reset;
}
break;
case PWM_OCNState_OffState:
{
/* OC3N = 0 OSSR = 1 and sets the polarity */
PWM->OMR2 &= PWM_OC3N_Disable;
DTR_REG |= PWM_OSSR_Set;
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
{
PWM->OMR2 |= PWM_OC3NP_Set;
}
else
{
PWM->OMR2 &= PWM_OC3NP_Reset;
}
}
break;
}
} /* End not complementary case */
}/* end channel 3 */
if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable)
{
DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency |
PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState;
PWM->DTR = DTR_REG;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
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