filter.tan.qmsg

matlab在fpga中的应用的三个具体事例

{ "Info" "ITDB_FULL_TCO_RESULT" "g_clk test_coefout\[9\] filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232 18.076 ns memory " "Info: tco from clock \"g_clk\" to destination pin \"test_coefout\[9\]\" through memory \"filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232\" is 18.076 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk source 5.236 ns + Longest memory " "Info: + Longest clock path from clock \"g_clk\" to source memory is 5.236 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns g_clk 1 CLK PIN_AA35 3774 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AA35; Fanout = 3774; CLK Node = 'g_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { g_clk } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.598 ns) + CELL(0.639 ns) 5.236 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232 2 MEM M4K_X73_Y78 1 " "Info: 2: + IC(3.598 ns) + CELL(0.639 ns) = 5.236 ns; Loc. = M4K_X73_Y78; Fanout = 1; MEM Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.237 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } "NODE_NAME" } } { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 4688 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 31.28 % ) " "Info: Total cell delay = 1.638 ns ( 31.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.598 ns ( 68.72 % ) " "Info: Total interconnect delay = 3.598 ns ( 68.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.236 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.236 ns" { g_clk g_clk~out0 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } { 0.000ns 0.000ns 3.598ns } { 0.000ns 0.999ns 0.639ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.537 ns + " "Info: + Micro clock to output delay of source is 0.537 ns" {  } { { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 4688 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.303 ns + Longest memory pin " "Info: + Longest memory to pin delay is 12.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.090 ns) 0.090 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232 1 MEM M4K_X73_Y78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.090 ns) = 0.090 ns; Loc. = M4K_X73_Y78; Fanout = 1; MEM Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a232'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } "NODE_NAME" } } { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 4688 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.283 ns) + CELL(0.100 ns) 3.473 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result2152w~52 2 COMB LC_X54_Y52_N6 1 " "Info: 2: + IC(3.283 ns) + CELL(0.100 ns) = 3.473 ns; Loc. = LC_X54_Y52_N6; Fanout = 1; COMB Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result2152w~52'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.383 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 } "NODE_NAME" } } { "db/mux_8fb.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/mux_8fb.tdf" 187 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.100 ns) 3.962 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|_~31 3 COMB LC_X54_Y52_N5 2 " "Info: 3: + IC(0.389 ns) + CELL(0.100 ns) = 3.962 ns; Loc. = LC_X54_Y52_N5; Fanout = 2; COMB Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|_~31'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.489 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 } "NODE_NAME" } } { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.527 ns) 5.540 ns accumulator:shift_add\|accum\[10\]~COMBOUT 4 COMB LC_X58_Y52_N9 4 " "Info: 4: + IC(1.051 ns) + CELL(0.527 ns) = 5.540 ns; Loc. = LC_X58_Y52_N9; Fanout = 4; COMB Node = 'accumulator:shift_add\|accum\[10\]~COMBOUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 accumulator:shift_add|accum[10]~COMBOUT } "NODE_NAME" } } { "accumulator.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/accumulator.tdf" 31 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.117 ns) + CELL(2.646 ns) 12.303 ns test_coefout\[9\] 5 PIN PIN_A21 0 " "Info: 5: + IC(4.117 ns) + CELL(2.646 ns) = 12.303 ns; Loc. = PIN_A21; Fanout = 0; PIN Node = 'test_coefout\[9\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.763 ns" { accumulator:shift_add|accum[10]~COMBOUT test_coefout[9] } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 29 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.463 ns ( 28.15 % ) " "Info: Total cell delay = 3.463 ns ( 28.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.840 ns ( 71.85 % ) " "Info: Total interconnect delay = 8.840 ns ( 71.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.303 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 accumulator:shift_add|accum[10]~COMBOUT test_coefout[9] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.303 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 accumulator:shift_add|accum[10]~COMBOUT test_coefout[9] } { 0.000ns 3.283ns 0.389ns 1.051ns 4.117ns } { 0.090ns 0.100ns 0.100ns 0.527ns 2.646ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.236 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.236 ns" { g_clk g_clk~out0 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 } { 0.000ns 0.000ns 3.598ns } { 0.000ns 0.999ns 0.639ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.303 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 accumulator:shift_add|accum[10]~COMBOUT test_coefout[9] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.303 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result2152w~52 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|_~31 accumulator:shift_add|accum[10]~COMBOUT test_coefout[9] } { 0.000ns 3.283ns 0.389ns 1.051ns 4.117ns } { 0.090ns 0.100ns 0.100ns 0.527ns 2.646ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "filter_shift:shift_reg\|shifter_ff\[1\]\[6\] xin\[6\] g_clk -3.669 ns register " "Info: th for register \"filter_shift:shift_reg\|shifter_ff\[1\]\[6\]\" (data pin = \"xin\[6\]\", clock pin = \"g_clk\") is -3.669 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk destination 5.287 ns + Longest register " "Info: + Longest clock path from clock \"g_clk\" to destination register is 5.287 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns g_clk 1 CLK PIN_AA35 3774 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AA35; Fanout = 3774; CLK Node = 'g_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { g_clk } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.644 ns) + CELL(0.644 ns) 5.287 ns filter_shift:shift_reg\|shifter_ff\[1\]\[6\] 2 REG LC_X70_Y51_N7 2 " "Info: 2: + IC(3.644 ns) + CELL(0.644 ns) = 5.287 ns; Loc. = LC_X70_Y51_N7; Fanout = 2; REG Node = 'filter_shift:shift_reg\|shifter_ff\[1\]\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.288 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 31.08 % ) " "Info: Total cell delay = 1.643 ns ( 31.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.644 ns ( 68.92 % ) " "Info: Total interconnect delay = 3.644 ns ( 68.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.287 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.287 ns" { g_clk g_clk~out0 filter_shift:shift_reg|shifter_ff[1][6] } { 0.000ns 0.000ns 3.644ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destination is 0.114 ns" {  } { { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.070 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.312 ns) 1.312 ns xin\[6\] 1 PIN PIN_H18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.312 ns) = 1.312 ns; Loc. = PIN_H18; Fanout = 1; PIN Node = 'xin\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { xin[6] } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 27 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.655 ns) + CELL(0.103 ns) 9.070 ns filter_shift:shift_reg\|shifter_ff\[1\]\[6\] 2 REG LC_X70_Y51_N7 2 " "Info: 2: + IC(7.655 ns) + CELL(0.103 ns) = 9.070 ns; Loc. = LC_X70_Y51_N7; Fanout = 2; REG Node = 'filter_shift:shift_reg\|shifter_ff\[1\]\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.758 ns" { xin[6] filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.415 ns ( 15.60 % ) " "Info: Total cell delay = 1.415 ns ( 15.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.655 ns ( 84.40 % ) " "Info: Total interconnect delay = 7.655 ns ( 84.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.070 ns" { xin[6] filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.070 ns" { xin[6] xin[6]~out0 filter_shift:shift_reg|shifter_ff[1][6] } { 0.000ns 0.000ns 7.655ns } { 0.000ns 1.312ns 0.103ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.287 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.287 ns" { g_clk g_clk~out0 filter_shift:shift_reg|shifter_ff[1][6] } { 0.000ns 0.000ns 3.644ns } { 0.000ns 0.999ns 0.644ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.070 ns" { xin[6] filter_shift:shift_reg|shifter_ff[1][6] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.070 ns" { xin[6] xin[6]~out0 filter_shift:shift_reg|shifter_ff[1][6] } { 0.000ns 0.000ns 7.655ns } { 0.000ns 1.312ns 0.103ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 15:46:26 2007 " "Info: Processing ended: Mon Dec 10 15:46:26 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}